testmem.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 35 行

// test file for MEM unit
module testmem;
wire [31:0] MEMDataOut;
reg clk;
reg  M_WriteMem;
reg [31:0]M_ALUResult,M_B;
MEM MEM(
//input
	.clk(clk),
	.M_WriteMem(M_WriteMem),
	.M_ALUResult(M_ALUResult),
	.M_B(M_B),
//output
	.MEMDataOut(MEMDataOut)
	);	
initial
begin
	clk = 1;
	M_ALUResult=0;
	M_WriteMem = 1;
	M_B = 0;
	$monitor($time,"M_ALUResult= %d,MEMDataOut= %d\n",M_ALUResult,MEMDataOut);
	#20 	M_ALUResult=1;
	#20 M_ALUResult=2;
	#20 M_ALUResult=3;
	#20 	M_ALUResult=4;
end


	

always 
#10 clk = ~clk;

endmodule