testid.v

用VHDL设计具有简单MIPS功能的源码

//test file for ID unit
module testid;
reg clk;
reg [31:0] D_IR,D_NPC;
reg W_WriteReg;
reg [4:0] W_RegWriteAddr;
reg [31:0] W_RegWriteData;

wire WritePC,Branch,WriteIR,ReadMem,WriteReg,MemToReg,WriteMem;
wire [3:0] ALUcontrol;
wire regDes;
wire ALUSrcB;
wire[1:0] FWDB,FWDA;
wire [31:0] BranchAddr;
wire [31:0] ea,eb,ei;
wire [4:0] ert,erd;

ID ID(		//input
			.clk(clk),
			.D_IR(D_IR),
			.D_NPC(D_NPC),
			.W_WriteReg(W_WriteReg),
			.W_RegWriteAddr(W_RegWriteAddr),
			.W_RegWriteData(W_RegWriteData),
			//output
			.WritePC(WritePC),
			.Branch(Branch),
			.WriteIR(WriteIR),
			.ReadMem(ReadMem),
			.WriteReg(WriteReg),
			.MemToReg(MemToReg),
			.WriteMem(WriteMem),
			.ALUcontrol(ALUcontrol),
			.RegDes(RegDes),
			.ALUSrcB(ALUSrcB),
			.FWDB(FWDB),
			.FWDA(FWDA),
			.BranchAddr(BranchAddr),
			.ea(ea),
			.eb(eb),
			.ei(ei),
			.ert(ert),
			.erd(erd)
			);
	initial 
	begin
		clk = 0;
		D_IR = 0;
		D_NPC = 0;
		W_WriteReg = 1;
		W_RegWriteAddr = 31;
		W_RegWriteData = 22;
	end
	always
	begin
	 #10 clk = ~clk;
	end
	always
	begin 
   		$monitor($time,"D_IR= %x,ALUcontrol = %b,WritePC = %b ,ea = %x,eb = %x ,ei = %x\n",D_IR,ALUcontrol,WritePC,ea,eb,ei);
		#20 D_IR = 32'h00641820; 
		#20 D_IR = 32'h20020004;
		#20 D_IR = 32'h00001820;
		#20 D_IR = 32'h8C240000;
	end
endmodule