testif.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 36 行

//test file for IF unit
module testif;
reg clk,rst,Branch,WritePC;
wire[31:0] pc,instr,D_IR,D_NPC;
wire [31:0] BranchAddr;

	IF IF (
		// Outputs
		.pc				(pc),        
		.instr			(instr),
		// Inputs
		.clk			(clk),
		.rst			(rst),
		.Branch			(Branch), 
		.WritePC 		(WritePC),
		.BranchAddr		(BranchAddr)
	);

	assign WriteIR = 1;
	dffre D1(.clk(clk), .d(instr), .q(D_IR), .en(WriteIR));
	dffre D2(.clk(clk), .d(pc), .q(D_NPC), .en(WriteIR));
		
always
 #10 clk =~clk;

  initial
  begin
	Branch = 0;
	WritePC = 1;
	clk=0;rst=1;
   	$monitor($time,"pc= %d,instr = %x,D_NPC= %d,D_IR = %x \n",pc,instr,D_NPC,D_IR);
	#100 rst=0;
    #400 $finish;
  end

endmodule