mipstest.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 26 行

// test file for mips
module mipstest;
reg	clk;
reg	rst;
wire[31:0]	D_NPC;
wire[31:0]	D_IR;
wire[31:0]	ALUResult;
wire[31:0]	MEMDataOut;
MIPS MIPS (
	clk,
	rst,
	D_NPC,
	D_IR,
	ALUResult,
	MEMDataOut
);
always
 #10 clk =~clk;

  initial
  begin
	clk=0;rst=1;
//   	$monitor($time,"	pc=%d,D_NPC=%d,	D_IR=%x,E_ReadMem=%b,E_WriteReg=%b,E_MemToReg=%b,E_WriteMem=%b,E_RegDes=%b,E_ALUSrcB=%b,E_ALUcontrol=%d,E_RT=%d,E_RD=%d,E_A=%d,E_B=%d,Branch=%d,E_I=%d\n",pc,	D_NPC,	D_IR,	E_ReadMem,	E_WriteReg,	E_MemToReg,	E_WriteMem,	E_RegDes,	E_ALUSrcB,	E_ALUcontrol,	E_RT,	E_RD,	E_A,	E_B,Branch,	E_I);
	#100 rst=0;
  end
endmodule