_primary.vhd

用VHDL设计具有简单MIPS功能的源码

library verilog;
use verilog.vl_types.all;
entity ID is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        D_IR            : in     vl_logic_vector(31 downto 0);
        D_NPC           : in     vl_logic_vector(31 downto 0);
        E_WriteReg      : in     vl_logic;
        E_RD            : in     vl_logic_vector(4 downto 0);
        E_Result        : in     vl_logic_vector(31 downto 0);
        M_WriteReg      : in     vl_logic;
        M_RD            : in     vl_logic_vector(4 downto 0);
        M_Result        : in     vl_logic_vector(31 downto 0);
        W_WriteReg      : in     vl_logic;
        W_RegWriteAddr  : in     vl_logic_vector(4 downto 0);
        W_RegWriteData  : in     vl_logic_vector(31 downto 0);
        WritePC         : out    vl_logic;
        Branch          : out    vl_logic;
        WriteIR         : out    vl_logic;
        ReadMem         : out    vl_logic;
        WriteReg        : out    vl_logic;
        MemToReg        : out    vl_logic;
        WriteMem        : out    vl_logic;
        ALUcontrol      : out    vl_logic_vector(3 downto 0);
        RegDes          : out    vl_logic;
        ALUSrcB         : out    vl_logic;
        FWDB            : out    vl_logic_vector(1 downto 0);
        FWDA            : out    vl_logic_vector(1 downto 0);
        BranchAddr      : out    vl_logic_vector(31 downto 0);
        ea              : out    vl_logic_vector(31 downto 0);
        eb              : out    vl_logic_vector(31 downto 0);
        ei              : out    vl_logic_vector(31 downto 0);
        ert             : out    vl_logic_vector(4 downto 0);
        erd             : out    vl_logic_vector(4 downto 0)
    );
end ID;