regfile.v

来自「用VHDL设计具有简单MIPS功能的源码」· Verilog 代码 · 共 46 行

//******************************************************************************
// RegFile.v
//
// Contains the  register file
//
//
//******************************************************************************

module RegFile (
	// Outputs
	RsData, RtData,  

	// Inputs
	clk, RegWriteData, RegWriteAddr, RegWriteEn, RsAddr, RtAddr
);

	input		clk;
	// Info for register write port
	input [31:0]	RegWriteData;
	input [4:0]	RegWriteAddr;
	input		RegWriteEn;
	input [4:0]	RsAddr, RtAddr;
	// Data from register read ports
	output [31:0]	RsData;		// data output for read port A
	output [31:0]	RtData;		// data output for read port B

	reg [31:0]	regs [0:31];

//******************************************************************************
// get data from read registers
//******************************************************************************

	assign RsData = (RsAddr == 5'b0) ? 32'b0 : regs[RsAddr];
	assign RtData = (RtAddr == 5'b0) ? 32'b0 : regs[RtAddr];

//******************************************************************************
// write to register if necessary 
//******************************************************************************
	always @ (negedge clk) 
	begin
		if (RegWriteEn)
			regs[RegWriteAddr] <= RegWriteData;
	end


endmodule