div_2n.tan.rpt

此程序实现的是任意进制的分频 进制的输入是任意选择的

+-----------------------------------------------------------------------------------+
; Minimum tco                                                                       ;
+------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From     ; To    ; From Clock ;
+---------------+------------------+----------------+----------+-------+------------+
; N/A           ; None             ; 9.500 ns       ; clk_temp ; div2n ; clk        ;
+---------------+------------------+----------------+----------+-------+------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Nov 20 15:27:11 2008
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off div_2n -c div_2n
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 85.47 MHz between source register lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] and destination register lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] (period= 11.7 ns)
    Info: + Longest register to register delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
        Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'i~41'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 6.300 ns; Loc. = LC1_B19; Fanout = 9; COMB Node = 'i~45'
        Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 9.500 ns; Loc. = LC1_B13; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 5.200 ns ( 54.74 % )
        Info: Total interconnect delay = 4.300 ns ( 45.26 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B13; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock clk to source register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] (data pin = p[0], clock pin = clk) is 16.600 ns
    Info: + Longest pin to register delay is 19.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_3; Fanout = 2; PIN Node = 'p[0]'
        Info: 2: + IC(2.800 ns) + CELL(0.900 ns) = 6.800 ns; Loc. = LC1_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 7.000 ns; Loc. = LC2_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 7.200 ns; Loc. = LC3_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 7.400 ns; Loc. = LC4_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 7.600 ns; Loc. = LC5_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 7.800 ns; Loc. = LC6_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 8.000 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 9: + IC(0.000 ns) + CELL(1.100 ns) = 9.100 ns; Loc. = LC8_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7]'
        Info: 10: + IC(2.500 ns) + CELL(1.900 ns) = 13.500 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'i~41'
        Info: 11: + IC(0.600 ns) + CELL(1.900 ns) = 16.000 ns; Loc. = LC1_B19; Fanout = 9; COMB Node = 'i~45'
        Info: 12: + IC(1.800 ns) + CELL(1.400 ns) = 19.200 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
        Info: Total cell delay = 11.500 ns ( 59.90 % )
        Info: Total interconnect delay = 7.700 ns ( 40.10 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock clk to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock clk to destination pin div2n through register clk_temp is 9.500 ns
    Info: + Longest clock path from clock clk to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = Pin_53; Fanout = 0; PIN Node = 'div2n'
        Info: Total cell delay = 3.900 ns ( 82.98 % )
        Info: Total interconnect delay = 0.800 ns ( 17.02 % )
Info: th for register clk_temp (data pin = p[6], clock pin = clk) is -8.000 ns
    Info: + Longest clock path from clock clk to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 13.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_10; Fanout = 2; PIN Node = 'p[6]'
        Info: 2: + IC(2.900 ns) + CELL(1.900 ns) = 7.900 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]'
        Info: 3: + IC(2.500 ns) + CELL(1.400 ns) = 11.800 ns; Loc. = LC6_B19; Fanout = 2; COMB Node = 'i~44'
        Info: 4: + IC(0.600 ns) + CELL(0.900 ns) = 13.300 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: Total cell delay = 7.300 ns ( 54.89 % )
        Info: Total interconnect delay = 6.000 ns ( 45.11 % )
Info: Minimum tco from clock clk to destination pin div2n through register clk_temp is 9.500 ns
    Info: + Shortest clock path from clock clk to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Shortest register to pin delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'
        Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = Pin_53; Fanout = 0; PIN Node = 'div2n'
        Info: Total cell delay = 3.900 ns ( 82.98 % )
        Info: Total interconnect delay = 0.800 ns ( 17.02 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 20 15:27:14 2008
    Info: Elapsed time: 00:00:02