prev_cmp_div_2n.map.qmsg

此程序实现的是任意进制的分频 进制的输入是任意选择的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 19 23:58:25 2008 " "Info: Processing started: Wed Nov 19 23:58:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off div_2n -c div_2n " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div_2n -c div_2n" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_2n.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div_2n.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div_2n-one " "Info: Found design unit 1: div_2n-one" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 div_2n " "Info: Found entity 1: div_2n" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "div_2n " "Info: Elaborating entity \"div_2n\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "m div_2n.vhd(14) " "Warning (10631): VHDL Process Statement warning at div_2n.vhd(14): inferring latch(es) for signal or variable \"m\", which holds its previous value in one or more paths through the process" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[0\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[0\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[1\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[1\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[2\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[2\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[3\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[3\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[4\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[4\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[5\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[5\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[6\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[6\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "m\[7\] div_2n.vhd(14) " "Info (10041): Inferred latch for \"m\[7\]\" at div_2n.vhd(14)" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~8 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"cnt\[0\]~8\"" {  } { { "div_2n.vhd" "cnt\[0\]~8" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 268 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"lpm_counter:cnt_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 425 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:cnt_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:cnt_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "m\[0\] " "Warning: Latch m\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal p\[4\]" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "m\[1\] " "Warning: Latch m\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal p\[4\]" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "m\[2\] " "Warning: Latch m\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal p\[4\]" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "m\[3\] " "Warning: Latch m\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal p\[4\]" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "set " "Warning (15610): No output dependent on input pin \"set\"" {  } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "27 " "Info: Implemented 27 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 19 23:58:38 2008 " "Info: Processing ended: Wed Nov 19 23:58:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}