div_2n.csf.qmsg

此程序实现的是任意进制的分频 进制的输入是任意选择的

{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 85.47 MHz 11.7 ns Internal " "Info: Clock clk has Internal fmax of 85.47 MHz between source register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] and destination register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] (period= 11.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register register " "Info: + Longest register to register delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC8_B13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 3.800 ns i~41 2 COMB LC3_B19 2 " "Info: 2: + IC(1.900 ns) + CELL(1.900 ns) = 3.800 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'i~41'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.800 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] i~41 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 6.300 ns i~45 3 COMB LC1_B19 9 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 6.300 ns; Loc. = LC1_B19; Fanout = 9; COMB Node = 'i~45'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.500 ns" { i~41 i~45 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 9.500 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC1_B13 3 " "Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 9.500 ns; Loc. = LC1_B13; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.200 ns" { i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns 54.74 % " "Info: Total cell delay = 5.200 ns ( 54.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns 45.26 % " "Info: Total interconnect delay = 4.300 ns ( 45.26 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "9.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] i~41 i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_B13 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B13; Fanout = 3; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_B13 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "9.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] i~41 i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] p\[0\] clk 16.600 ns register " "Info: tsu for register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] (data pin = p\[0\], clock pin = clk) is 16.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.200 ns + Longest pin register " "Info: + Longest pin to register delay is 19.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns p\[0\] 1 PIN Pin_3 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_3; Fanout = 2; PIN Node = 'p\[0\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { p[0] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.900 ns) 6.800 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\] 2 COMB LC1_B10 2 " "Info: 2: + IC(2.800 ns) + CELL(0.900 ns) = 6.800 ns; Loc. = LC1_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[0\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.700 ns" { p[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.000 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 3 COMB LC2_B10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 7.000 ns; Loc. = LC2_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.200 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 4 COMB LC3_B10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 7.200 ns; Loc. = LC3_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.400 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 5 COMB LC4_B10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 7.400 ns; Loc. = LC4_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.600 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 6 COMB LC5_B10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 7.600 ns; Loc. = LC5_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 7.800 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 7 COMB LC6_B10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 7.800 ns; Loc. = LC6_B10; Fanout = 2; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.000 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 8 COMB LC7_B10 1 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 8.000 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "0.200 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 9.100 ns lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[7\] 9 COMB LC8_B10 1 " "Info: 9: + IC(0.000 ns) + CELL(1.100 ns) = 9.100 ns; Loc. = LC8_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[7\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "1.100 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/addcore.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.900 ns) 13.500 ns i~41 10 COMB LC3_B19 2 " "Info: 10: + IC(2.500 ns) + CELL(1.900 ns) = 13.500 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'i~41'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.400 ns" { lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~41 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 16.000 ns i~45 11 COMB LC1_B19 9 " "Info: 11: + IC(0.600 ns) + CELL(1.900 ns) = 16.000 ns; Loc. = LC1_B19; Fanout = 9; COMB Node = 'i~45'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.500 ns" { i~41 i~45 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 19.200 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 12 REG LC8_B13 2 " "Info: 12: + IC(1.800 ns) + CELL(1.400 ns) = 19.200 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.200 ns" { i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.500 ns 59.90 % " "Info: Total cell delay = 11.500 ns ( 59.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns 40.10 % " "Info: Total interconnect delay = 7.700 ns ( 40.10 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "19.200 ns" { p[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~41 i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_B13 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B13; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "19.200 ns" { p[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[7] i~41 i~45 lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk div2n clk_temp 9.500 ns register " "Info: tco from clock clk to destination pin div2n through register clk_temp is 9.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC2_B19 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register pin " "Info: + Longest register to pin delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_temp 1 REG LC2_B19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 4.700 ns div2n 2 PIN Pin_53 0 " "Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = Pin_53; Fanout = 0; PIN Node = 'div2n'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 82.98 % " "Info: Total cell delay = 3.900 ns ( 82.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 17.02 % " "Info: Total interconnect delay = 0.800 ns ( 17.02 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "clk_temp p\[6\] clk -8.000 ns register " "Info: th for register clk_temp (data pin = p\[6\], clock pin = clk) is -8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC2_B19 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns p\[6\] 1 PIN Pin_10 2 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_10; Fanout = 2; PIN Node = 'p\[6\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { p[6] } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.900 ns) 7.900 ns lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\] 2 COMB LC7_B10 1 " "Info: 2: + IC(2.900 ns) + CELL(1.900 ns) = 7.900 ns; Loc. = LC7_B10; Fanout = 1; COMB Node = 'lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.800 ns" { p[6] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.400 ns) 11.800 ns i~44 3 COMB LC6_B19 2 " "Info: 3: + IC(2.500 ns) + CELL(1.400 ns) = 11.800 ns; Loc. = LC6_B19; Fanout = 2; COMB Node = 'i~44'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] i~44 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 13.300 ns clk_temp 4 REG LC2_B19 1 " "Info: 4: + IC(0.600 ns) + CELL(0.900 ns) = 13.300 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "1.500 ns" { i~44 clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns 54.89 % " "Info: Total cell delay = 7.300 ns ( 54.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 45.11 % " "Info: Total interconnect delay = 6.000 ns ( 45.11 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "13.300 ns" { p[6] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] i~44 clk_temp } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "13.300 ns" { p[6] lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] i~44 clk_temp } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk div2n clk_temp 9.500 ns register " "Info: Minimum tco from clock clk to destination pin div2n through register clk_temp is 9.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC2_B19 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_temp 1 REG LC2_B19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 4.700 ns div2n 2 PIN Pin_53 0 " "Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = Pin_53; Fanout = 0; PIN Node = 'div2n'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 82.98 % " "Info: Total cell delay = 3.900 ns ( 82.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 17.02 % " "Info: Total interconnect delay = 0.800 ns ( 17.02 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 20 15:27:14 2008 " "Info: Processing ended: Thu Nov 20 15:27:14 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 1  " "Info: Quartus II Full Compilation was successful. 0 errors, 1 warning" {  } {  } 0}