div_2n.tan.qmsg

此程序实现的是任意进制的分频 进制的输入是任意选择的

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk div2n clk_temp 9.500 ns register " "Info: Minimum tco from clock clk to destination pin div2n through register clk_temp is 9.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_44 10 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 10; CLK Node = 'clk'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC2_B19 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_temp 1 REG LC2_B19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B19; Fanout = 1; REG Node = 'clk_temp'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "" { clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 4.700 ns div2n 2 PIN Pin_53 0 " "Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = Pin_53; Fanout = 0; PIN Node = 'div2n'" {  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/div_2n.vhd" "" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 82.98 % " "Info: Total cell delay = 3.900 ns ( 82.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 17.02 % " "Info: Total interconnect delay = 0.800 ns ( 17.02 % )" {  } {  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}  } { { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } } { "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" "" "" { Report "I:/myprg/Myprg/div_2n/db/div_2n_cmp.qrpt" Compiler "div_2n" "UNKNOWN" "V1" "I:/myprg/Myprg/div_2n/db/div_2n.quartus_db" { Floorplan "" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 20 15:27:14 2008 " "Info: Processing ended: Thu Nov 20 15:27:14 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}