📄 prev_cmp_div_2n.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 78.74 MHz 12.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.74 MHz between source register \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" and destination register \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (period= 12.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.500 ns + Longest register register " "Info: + Longest register to register delay is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC8_B14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B14; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 3.200 ns Equal0~84 2 COMB LC3_B13 1 " "Info: 2: + IC(1.800 ns) + CELL(1.400 ns) = 3.200 ns; Loc. = LC3_B13; Fanout = 1; COMB Node = 'Equal0~84'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~84 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 4.000 ns Equal0~86 3 COMB LC4_B13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.000 ns; Loc. = LC4_B13; Fanout = 1; COMB Node = 'Equal0~86'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { Equal0~84 Equal0~86 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 5.300 ns Equal0~78 4 COMB LC5_B13 2 " "Info: 4: + IC(0.000 ns) + CELL(1.300 ns) = 5.300 ns; Loc. = LC5_B13; Fanout = 2; COMB Node = 'Equal0~78'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { Equal0~86 Equal0~78 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 7.300 ns Equal0~78_wirecell 5 COMB LC1_B13 8 " "Info: 5: + IC(0.600 ns) + CELL(1.400 ns) = 7.300 ns; Loc. = LC1_B13; Fanout = 8; COMB Node = 'Equal0~78_wirecell'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Equal0~78 Equal0~78_wirecell } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 10.500 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 6 REG LC2_B14 4 " "Info: 6: + IC(1.800 ns) + CELL(1.400 ns) = 10.500 ns; Loc. = LC2_B14; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 60.00 % ) " "Info: Total cell delay = 6.300 ns ( 60.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 40.00 % ) " "Info: Total interconnect delay = 4.200 ns ( 40.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~84 Equal0~86 Equal0~78 Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} Equal0~84 {} Equal0~86 {} Equal0~78 {} Equal0~78_wirecell {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 1.800ns 0.000ns 0.000ns 0.600ns 1.800ns } { 0.000ns 1.400ns 0.800ns 1.300ns 1.400ns 1.400ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC2_B14 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B14; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_B14 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B14; Fanout = 2; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] Equal0~84 Equal0~86 Equal0~78 Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} Equal0~84 {} Equal0~86 {} Equal0~78 {} Equal0~78_wirecell {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 1.800ns 0.000ns 0.000ns 0.600ns 1.800ns } { 0.000ns 1.400ns 0.800ns 1.300ns 1.400ns 1.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[7] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] p\[3\] clk 22.200 ns register " "Info: tsu for register \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (data pin = \"p\[3\]\", clock pin = \"clk\") is 22.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.800 ns + Longest pin register " "Info: + Longest pin to register delay is 24.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns p\[3\] 1 PIN PIN_7 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_7; Fanout = 5; PIN Node = 'p\[3\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { p[3] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.900 ns) 8.100 ns Mux1~45 2 COMB LC1_B12 1 " "Info: 2: + IC(3.100 ns) + CELL(1.900 ns) = 8.100 ns; Loc. = LC1_B12; Fanout = 1; COMB Node = 'Mux1~45'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { p[3] Mux1~45 } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.900 ns) 12.400 ns Mux1~46 3 COMB LC1_B4 8 " "Info: 3: + IC(2.400 ns) + CELL(1.900 ns) = 12.400 ns; Loc. = LC1_B4; Fanout = 8; COMB Node = 'Mux1~46'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { Mux1~45 Mux1~46 } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.900 ns) 16.300 ns m\[3\] 4 COMB LOOP LC8_B13 2 " "Info: 4: + IC(0.000 ns) + CELL(3.900 ns) = 16.300 ns; Loc. = LC8_B13; Fanout = 2; COMB LOOP Node = 'm\[3\]'" { { "Info" "ITDB_PART_OF_SCC" "m\[3\] LC8_B13 " "Info: Loc. = LC8_B13; Node \"m\[3\]\"" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[3] } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[3] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { Mux1~46 m[3] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 18.300 ns Equal0~86 5 COMB LC4_B13 1 " "Info: 5: + IC(0.600 ns) + CELL(1.400 ns) = 18.300 ns; Loc. = LC4_B13; Fanout = 1; COMB Node = 'Equal0~86'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { m[3] Equal0~86 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 19.600 ns Equal0~78 6 COMB LC5_B13 2 " "Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 19.600 ns; Loc. = LC5_B13; Fanout = 2; COMB Node = 'Equal0~78'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { Equal0~86 Equal0~78 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 21.600 ns Equal0~78_wirecell 7 COMB LC1_B13 8 " "Info: 7: + IC(0.600 ns) + CELL(1.400 ns) = 21.600 ns; Loc. = LC1_B13; Fanout = 8; COMB Node = 'Equal0~78_wirecell'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Equal0~78 Equal0~78_wirecell } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 24.800 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 8 REG LC2_B14 4 " "Info: 8: + IC(1.800 ns) + CELL(1.400 ns) = 24.800 ns; Loc. = LC2_B14; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.300 ns ( 65.73 % ) " "Info: Total cell delay = 16.300 ns ( 65.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.500 ns ( 34.27 % ) " "Info: Total interconnect delay = 8.500 ns ( 34.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "24.800 ns" { p[3] Mux1~45 Mux1~46 m[3] Equal0~86 Equal0~78 Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "24.800 ns" { p[3] {} p[3]~out {} Mux1~45 {} Mux1~46 {} m[3] {} Equal0~86 {} Equal0~78 {} Equal0~78_wirecell {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 3.100ns 2.400ns 0.000ns 0.600ns 0.000ns 0.600ns 1.800ns } { 0.000ns 3.100ns 1.900ns 1.900ns 3.900ns 1.400ns 1.300ns 1.400ns 1.400ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC2_B14 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B14; Fanout = 4; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "24.800 ns" { p[3] Mux1~45 Mux1~46 m[3] Equal0~86 Equal0~78 Equal0~78_wirecell lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "24.800 ns" { p[3] {} p[3]~out {} Mux1~45 {} Mux1~46 {} m[3] {} Equal0~86 {} Equal0~78 {} Equal0~78_wirecell {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 3.100ns 2.400ns 0.000ns 0.600ns 0.000ns 0.600ns 1.800ns } { 0.000ns 3.100ns 1.900ns 1.900ns 3.900ns 1.400ns 1.300ns 1.400ns 1.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk div2n clk_temp 9.500 ns register " "Info: tco from clock \"clk\" to destination pin \"div2n\" through register \"clk_temp\" is 9.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC5_B19 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B19; Fanout = 2; REG Node = 'clk_temp'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} clk_temp {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register pin " "Info: + Longest register to pin delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_temp 1 REG LC5_B19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B19; Fanout = 2; REG Node = 'clk_temp'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_temp } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 4.700 ns div2n 2 PIN PIN_53 0 " "Info: 2: + IC(0.800 ns) + CELL(3.900 ns) = 4.700 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'div2n'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 82.98 % ) " "Info: Total cell delay = 3.900 ns ( 82.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns ( 17.02 % ) " "Info: Total interconnect delay = 0.800 ns ( 17.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { clk_temp {} div2n {} } { 0.000ns 0.800ns } { 0.000ns 3.900ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} clk_temp {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { clk_temp div2n } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { clk_temp {} div2n {} } { 0.000ns 0.800ns } { 0.000ns 3.900ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "clk_temp p\[7\] clk -11.300 ns register " "Info: th for register \"clk_temp\" (data pin = \"p\[7\]\", clock pin = \"clk\") is -11.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_42 9 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 9; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_temp 2 REG LC5_B19 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_B19; Fanout = 2; REG Node = 'clk_temp'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk clk_temp } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} clk_temp {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" { } { { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 16.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns p\[7\] 1 PIN PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_11; Fanout = 1; PIN Node = 'p\[7\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { p[7] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.400 ns) 7.300 ns Mux1~46 2 COMB LC1_B4 8 " "Info: 2: + IC(2.800 ns) + CELL(1.400 ns) = 7.300 ns; Loc. = LC1_B4; Fanout = 8; COMB Node = 'Mux1~46'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.200 ns" { p[7] Mux1~46 } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.900 ns) 11.200 ns m\[1\] 3 COMB LOOP LC6_B13 2 " "Info: 3: + IC(0.000 ns) + CELL(3.900 ns) = 11.200 ns; Loc. = LC6_B13; Fanout = 2; COMB LOOP Node = 'm\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "m\[1\] LC6_B13 " "Info: Loc. = LC6_B13; Node \"m\[1\]\"" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { Mux1~46 m[1] } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 13.700 ns Equal0~78 4 COMB LC5_B13 2 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 13.700 ns; Loc. = LC5_B13; Fanout = 2; COMB Node = 'Equal0~78'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { m[1] Equal0~78 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.000 ns) 16.600 ns clk_temp 5 REG LC5_B19 2 " "Info: 5: + IC(1.900 ns) + CELL(1.000 ns) = 16.600 ns; Loc. = LC5_B19; Fanout = 2; REG Node = 'clk_temp'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { Equal0~78 clk_temp } "NODE_NAME" } } { "div_2n.vhd" "" { Text "I:/myprg/Myprg/div_2n/div_2n.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns ( 68.07 % ) " "Info: Total cell delay = 11.300 ns ( 68.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 31.93 % ) " "Info: Total interconnect delay = 5.300 ns ( 31.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.600 ns" { p[7] Mux1~46 m[1] Equal0~78 clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.600 ns" { p[7] {} p[7]~out {} Mux1~46 {} m[1] {} Equal0~78 {} clk_temp {} } { 0.000ns 0.000ns 2.800ns 0.000ns 0.600ns 1.900ns } { 0.000ns 3.100ns 1.400ns 3.900ns 1.900ns 1.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk {} clk~out {} clk_temp {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.600 ns" { p[7] Mux1~46 m[1] Equal0~78 clk_temp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.600 ns" { p[7] {} p[7]~out {} Mux1~46 {} m[1] {} Equal0~78 {} clk_temp {} } { 0.000ns 0.000ns 2.800ns 0.000ns 0.600ns 1.900ns } { 0.000ns 3.100ns 1.400ns 3.900ns 1.900ns 1.000ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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