div_2n.map.rpt

此程序实现的是任意进制的分频 进制的输入是任意选择的

           |-- a_csnbuffer:result_node
      |-- altshift:carry_ext_latency_ffs
      |-- altshift:oflow_ext_latency_ffs
      |-- altshift:result_ext_latency_ffs


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node             ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                               ;
+----------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
; |div_2n                                ; 22 (6)      ; 9         ; 0           ; 10   ; 13 (5)       ; 0 (0)             ; 9 (1)            ; 16 (0)          ; |div_2n                                                           ;
;    |lpm_add_sub:i_rtl_1|               ; 8 (0)       ; 0         ; 0           ; 0    ; 8 (0)        ; 0 (0)             ; 0 (0)            ; 8 (0)           ; |div_2n|lpm_add_sub:i_rtl_1                                       ;
;       |addcore:adder|                  ; 8 (1)       ; 0         ; 0           ; 0    ; 8 (1)        ; 0 (0)             ; 0 (0)            ; 8 (1)           ; |div_2n|lpm_add_sub:i_rtl_1|addcore:adder                         ;
;          |a_csnbuffer:result_node|     ; 7 (7)       ; 0         ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 7 (7)           ; |div_2n|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node ;
;    |lpm_counter:cnt_rtl_0|             ; 8 (0)       ; 8         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |div_2n|lpm_counter:cnt_rtl_0                                     ;
;       |alt_counter_f10ke:wysi_counter| ; 8 (8)       ; 8         ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |div_2n|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter      ;
+----------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in I:/myprg/Myprg/div_2n/div_2n.map.eqn.


+-----------------------------------------------------------------+
; Analysis & Synthesis Files Read                                 ;
+------------------------------------------------------------------
; File Name                                                ; Read ;
+----------------------------------------------------------+------+
; div_2n.vhd                                               ; Read ;
; c:/quartus/libraries/megafunctions/lpm_counter.tdf       ; Read ;
; c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ; Read ;
; c:/quartus/libraries/megafunctions/lpm_add_sub.tdf       ; Read ;
; c:/quartus/libraries/megafunctions/addcore.tdf           ; Read ;
; c:/quartus/libraries/megafunctions/a_csnbuffer.tdf       ; Read ;
; c:/quartus/libraries/megafunctions/altshift.tdf          ; Read ;
+----------------------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource                      ; Usage       ;
+-------------------------------+-------------+
; Logic cells                   ; 22          ;
; Total combinational functions ; 22          ;
; Total registers               ; 9           ;
; I/O pins                      ; 10          ;
; Maximum fan-out node          ; clk         ;
; Maximum fan-out               ; 9           ;
; Total fan-out                 ; 64          ;
; Average fan-out               ; 2.00        ;
+-------------------------------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 8     ;
; Number of synthesis-generated cells                    ; 14    ;
; Number of WYSIWYG LUTs                                 ; 8     ;
; Number of synthesis-generated LUTs                     ; 14    ;
; Number of WYSIWYG registers                            ; 8     ;
; Number of synthesis-generated registers                ; 1     ;
; Number of cells with combinational logic only          ; 13    ;
; Number of cells with registers only                    ; 0     ;
; Number of cells with combinational logic and registers ; 9     ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 8     ;
; Number of registers using SLOAD      ; 0     ;
; Number of registers using ACLR       ; 0     ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 0     ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Nov 20 15:26:42 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off div_2n -c div_2n
Info: Found 2 design units and 1 entities in source file div_2n.vhd
    Info: Found design unit 1: div_2n-one
    Info: Found entity 1: div_2n
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: cnt[0]~0
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Implemented 32 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 1 output pins
    Info: Implemented 22 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Nov 20 15:26:51 2008
    Info: Elapsed time: 00:00:08