prev_cmp_cnt_fry.tan.qmsg

本程序功能是由VHDL语言实现对频率的测量

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk0 scan\[3\] cnt6\[1\] 11.500 ns register " "Info: Minimum tco from clock \"clk0\" to destination pin \"scan\[3\]\" through register \"cnt6\[1\]\" is 11.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk0 1 CLK PIN_2 14 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_2; Fanout = 14; CLK Node = 'clk0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns cnt6\[1\] 2 REG LC8_B24 17 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_B24; Fanout = 17; REG Node = 'cnt6\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk0 cnt6[1] } "NODE_NAME" } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk0 cnt6[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk0 {} clk0~out {} cnt6[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6\[1\] 1 REG LC8_B24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B24; Fanout = 17; REG Node = 'cnt6\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt6[1] } "NODE_NAME" } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 2.000 ns Mux7~10 2 COMB LC6_B24 1 " "Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 2.000 ns; Loc. = LC6_B24; Fanout = 1; COMB Node = 'Mux7~10'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { cnt6[1] Mux7~10 } "NODE_NAME" } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(3.900 ns) 6.700 ns scan\[3\] 3 PIN PIN_80 0 " "Info: 3: + IC(0.800 ns) + CELL(3.900 ns) = 6.700 ns; Loc. = PIN_80; Fanout = 0; PIN Node = 'scan\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { Mux7~10 scan[3] } "NODE_NAME" } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 79.10 % ) " "Info: Total cell delay = 5.300 ns ( 79.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 20.90 % ) " "Info: Total interconnect delay = 1.400 ns ( 20.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { cnt6[1] Mux7~10 scan[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.700 ns" { cnt6[1] {} Mux7~10 {} scan[3] {} } { 0.000ns 0.600ns 0.800ns } { 0.000ns 1.400ns 3.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { clk0 cnt6[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.900 ns" { clk0 {} clk0~out {} cnt6[1] {} } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClos