prev_cmp_cnt_fry.tan.qmsg

本程序功能是由VHDL语言实现对频率的测量

{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "seg\[3\]\$latch " "Warning: Node \"seg\[3\]\$latch\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "seg\[2\]\$latch " "Warning: Node \"seg\[2\]\$latch\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "seg\[1\]\$latch " "Warning: Node \"seg\[1\]\$latch\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 71 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "4 " "Warning: Found combinational loop of 4 nodes" { { "Warning" "WTAN_SCC_NODE" "flag\[1\] " "Warning: Node \"flag\[1\]\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "flag~29 " "Warning: Node \"flag~29\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 14 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "Equal2~10 " "Warning: Node \"Equal2~10\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 37 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WTAN_SCC_NODE" "flag\[0\] " "Warning: Node \"flag\[0\]\"" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 -1 0 } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 14 -1 0 } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 37 -1 0 } } { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 31 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk0 " "Info: Assuming node \"clk0\" is an undefined clock" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "cnt_fry.vhd" "" { Text "J:/VHDL/myprg/Myprg/cnt_fry/cnt_fry.vhd" 5 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}