📄 timer.txt
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---------------------------------------------------------------------
-- Design unit: timer(display) (Entity and Architectures)
-- File name : timer.vhd
-- Description: 24 hours timer
-- Limitations: None
-- System : VHDL'93
-- Author : Fan Bishuang
-- Email : fbshfj@csust.edu.cn
-- Revision : Version 1.0 16/5/05
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity timer is
port(clk : in std_logic; -- System clock input port(250KHz).
L : out std_logic_vector(2 downto 0); -- 8 seven-segment displays selection ports.
dled: out std_logic_vector(7 downto 0)); -- Digits display ports.
end timer;
architecture display of timer is
begin
process (clk)
variable cnt: integer range 0 to 7; -- 8 seven-segment displays seletion counter.
variable ct:integer range 0 to 250000 ; -- 1 second generator counter.
variable hourH: integer range 0 to 2;
variable minuteH,secondH: integer range 0 to 6;
variable hourL,minuteL,secondL: integer range 0 to 10;
begin
if clk'event and clk = '1' then
cnt:=cnt+1;
ct:=ct+1;
if ct=250000 then -- 1 second
ct:=0;
secondL:=secondL+1;
end if;
if secondL=10 then -- 10 seconds
secondL:=0;
secondH:=secondH+1;
end if;
if secondH=6 then -- 60 seconds(1 minute)
secondH:=0;
minuteL:=minuteL+1;
end if;
if minuteL=10 then -- 10 minutes
minuteL:=0;
minuteH:=minuteH+1;
end if;
if minuteH=6 then -- 60 minutes(1 hour)
minuteH:=0;
hourL:=hourL+1;
end if;
if hourL=10 then -- 10 hours
hourL:=0;
hourH:=hourH+1;
end if;
if hourH=2 and hourL =4 then -- 24 hours
hourH:=0;
hourL:=0;
end if;
case cnt is -- To display the time.
when 0 => L<="000"; -- Enable the leftmost display.
case hourH is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when others => null;
end case;
when 1 => L<="001"; -- Enable the second display.
case hourL is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when 3 => dled<=X"F2";--3
when 4 => dled<=X"66";--4
when 5 => dled<=X"B6";--5
when 6 => dled<=X"BE";--6
when 7 => dled<=X"E0";--7
when 8 => dled<=X"FE";--8
when 9 => dled<=X"F6";--9
when others => null;
end case;
when 2 => L<="010"; -- Enable the third display.
dled<=X"00"; -- Blanked.
when 3 => L<="011"; -- Enable the fourth display.
case minuteH is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when 3 => dled<=X"F2";--3
when 4 => dled<=X"66";--4
when 5 => dled<=X"B6";--5
when others => null;
end case;
when 4 => L<="100"; -- Enable the fifth display.
case minuteL is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when 3 => dled<=X"F2";--3
when 4 => dled<=X"66";--4
when 5 => dled<=X"B6";--5
when 6 => dled<=X"BE";--6
when 7 => dled<=X"E0";--7
when 8 => dled<=X"FE";--8
when 9 => dled<=X"F6";--9
when others => null;
end case;
when 5 => L<="101"; -- Enable the sixth display.
dled<=X"00"; -- Blanked.
when 6 => L<="110"; -- Enable the seventh display.
case secondH is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when 3 => dled<=X"F2";--3
when 4 => dled<=X"66";--4
when 5 => dled<=X"B6";--5
when others => null;
end case;
when 7 => L<="111"; -- Enable the rightmost display
case secondL is
when 0 => dled<=X"FC";--0
when 1 => dled<=X"60";--1
when 2 => dled<=X"DA";--2
when 3 => dled<=X"F2";--3
when 4 => dled<=X"66";--4
when 5 => dled<=X"B6";--5
when 6 => dled<=X"BE";--6
when 7 => dled<=X"E0";--7
when 8 => dled<=X"FE";--8
when 9 => dled<=X"F6";--9
when others => null;
end case;
end case;
end if;
end process;
end display;
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