rl_shift.tan.qmsg

带有同步预置的加载左右移位寄存器VHDL源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register TEMP\[2\] TEMP\[3\] 304.04 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 304.04 MHz between source register \"TEMP\[2\]\" and destination register \"TEMP\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.198 ns + Longest register register " "Info: + Longest register to register delay is 2.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TEMP\[2\] 1 REG LC_X1_Y7_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N8; Fanout = 3; REG Node = 'TEMP\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TEMP[2] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.918 ns) + CELL(0.280 ns) 2.198 ns TEMP\[3\] 2 REG LC_X1_Y7_N9 3 " "Info: 2: + IC(1.918 ns) + CELL(0.280 ns) = 2.198 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'TEMP\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.198 ns" { TEMP[2] TEMP[3] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 12.74 % ) " "Info: Total cell delay = 0.280 ns ( 12.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.918 ns ( 87.26 % ) " "Info: Total interconnect delay = 1.918 ns ( 87.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.198 ns" { TEMP[2] TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.198 ns" { TEMP[2] TEMP[3] } { 0.000ns 1.918ns } { 0.000ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_H5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns TEMP\[3\] 2 REG LC_X1_Y7_N9 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'TEMP\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK TEMP[3] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.681 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_H5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns TEMP\[2\] 2 REG LC_X1_Y7_N8 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N8; Fanout = 3; REG Node = 'TEMP\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK TEMP[2] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.198 ns" { TEMP[2] TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.198 ns" { TEMP[2] TEMP[3] } { 0.000ns 1.918ns } { 0.000ns 0.280ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[3] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TEMP[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { TEMP[3] } {  } {  } } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "TEMP\[0\] MODE\[0\] CLK 3.536 ns register " "Info: tsu for register \"TEMP\[0\]\" (data pin = \"MODE\[0\]\", clock pin = \"CLK\") is 3.536 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.884 ns + Longest pin register " "Info: + Longest pin to register delay is 6.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns MODE\[0\] 1 PIN PIN_E4 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_E4; Fanout = 9; PIN Node = 'MODE\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { MODE[0] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.844 ns) + CELL(1.908 ns) 6.884 ns TEMP\[0\] 2 REG LC_X1_Y7_N7 2 " "Info: 2: + IC(3.844 ns) + CELL(1.908 ns) = 6.884 ns; Loc. = LC_X1_Y7_N7; Fanout = 2; REG Node = 'TEMP\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.752 ns" { MODE[0] TEMP[0] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.040 ns ( 44.16 % ) " "Info: Total cell delay = 3.040 ns ( 44.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.844 ns ( 55.84 % ) " "Info: Total interconnect delay = 3.844 ns ( 55.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.884 ns" { MODE[0] TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.884 ns" { MODE[0] MODE[0]~combout TEMP[0] } { 0.000ns 0.000ns 3.844ns } { 0.000ns 1.132ns 1.908ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.681 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_H5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns TEMP\[0\] 2 REG LC_X1_Y7_N7 2 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N7; Fanout = 2; REG Node = 'TEMP\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK TEMP[0] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.884 ns" { MODE[0] TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.884 ns" { MODE[0] MODE[0]~combout TEMP[0] } { 0.000ns 0.000ns 3.844ns } { 0.000ns 1.132ns 1.908ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DATAOUT\[4\] TEMP\[4\] 8.627 ns register " "Info: tco from clock \"CLK\" to destination pin \"DATAOUT\[4\]\" through register \"TEMP\[4\]\" is 8.627 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.681 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_H5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns TEMP\[4\] 2 REG LC_X1_Y7_N1 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK TEMP[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.570 ns + Longest register pin " "Info: + Longest register to pin delay is 4.570 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TEMP\[4\] 1 REG LC_X1_Y7_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TEMP[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.248 ns) + CELL(2.322 ns) 4.570 ns DATAOUT\[4\] 2 PIN PIN_G3 0 " "Info: 2: + IC(2.248 ns) + CELL(2.322 ns) = 4.570 ns; Loc. = PIN_G3; Fanout = 0; PIN Node = 'DATAOUT\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.570 ns" { TEMP[4] DATAOUT[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 50.81 % ) " "Info: Total cell delay = 2.322 ns ( 50.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.248 ns ( 49.19 % ) " "Info: Total interconnect delay = 2.248 ns ( 49.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.570 ns" { TEMP[4] DATAOUT[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.570 ns" { TEMP[4] DATAOUT[4] } { 0.000ns 2.248ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.570 ns" { TEMP[4] DATAOUT[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.570 ns" { TEMP[4] DATAOUT[4] } { 0.000ns 2.248ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "TEMP\[4\] DATAIN\[4\] CLK -1.288 ns register " "Info: th for register \"TEMP\[4\]\" (data pin = \"DATAIN\[4\]\", clock pin = \"CLK\") is -1.288 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.681 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_H5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns TEMP\[4\] 2 REG LC_X1_Y7_N1 3 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.518 ns" { CLK TEMP[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.190 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns DATAIN\[4\] 1 PIN PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_H2; Fanout = 1; PIN Node = 'DATAIN\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATAIN[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.467 ns) + CELL(0.591 ns) 5.190 ns TEMP\[4\] 2 REG LC_X1_Y7_N1 3 " "Info: 2: + IC(3.467 ns) + CELL(0.591 ns) = 5.190 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.058 ns" { DATAIN[4] TEMP[4] } "NODE_NAME" } } { "RL_SHIFT.vhd" "" { Text "D:/altera/quartus60/实例/同步加载左右移位寄存器/RL_SHIFT.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 33.20 % ) " "Info: Total cell delay = 1.723 ns ( 33.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.467 ns ( 66.80 % ) " "Info: Total interconnect delay = 3.467 ns ( 66.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.190 ns" { DATAIN[4] TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.190 ns" { DATAIN[4] DATAIN[4]~combout TEMP[4] } { 0.000ns 0.000ns 3.467ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.681 ns" { CLK TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.681 ns" { CLK CLK~combout TEMP[4] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.190 ns" { DATAIN[4] TEMP[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.190 ns" { DATAIN[4] DATAIN[4]~combout TEMP[4] } { 0.000ns 0.000ns 3.467ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 22 23:58:55 2008 " "Info: Processing ended: Mon Dec 22 23:58:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}