rl_shift.vhd

带有同步预置的加载左右移位寄存器VHDL源代码

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY RL_SHIFT IS
 PORT( CLK,RESET: IN STD_LOGIC;
       MODE :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       DATAIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       RIGHT,LEFT:IN STD_LOGIC;
       DATAOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY RL_SHIFT;

ARCHITECTURE ONE OF RL_SHIFT IS
SIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK,RESET,MODE,DATAIN,RIGHT,LEFT,TEMP)
 
 BEGIN
  IF RISING_EDGE(CLK) THEN
    IF (RESET='1') THEN
        TEMP<="00000000";
    ELSE
      
      CASE MODE IS
         WHEN "01"=>TEMP<=RIGHT&TEMP(7 DOWNTO 1);
         WHEN "10"=>TEMP<=TEMP(6 DOWNTO 0)&LEFT;
         WHEN "11"=>TEMP<=DATAIN;
         WHEN OTHERS=>NULL;
     END CASE;
   END IF;
END IF;
  DATAOUT<=TEMP; 
END PROCESS;
  
END ARCHITECTURE ONE;