rl_shift.tan.rpt

带有同步预置的加载左右移位寄存器VHDL源代码

; N/A   ; None         ; 2.048 ns   ; LEFT      ; TEMP[0] ; CLK      ;
; N/A   ; None         ; 1.978 ns   ; RIGHT     ; TEMP[7] ; CLK      ;
; N/A   ; None         ; 1.946 ns   ; DATAIN[1] ; TEMP[1] ; CLK      ;
; N/A   ; None         ; 1.940 ns   ; DATAIN[2] ; TEMP[2] ; CLK      ;
; N/A   ; None         ; 1.907 ns   ; DATAIN[7] ; TEMP[7] ; CLK      ;
; N/A   ; None         ; 1.842 ns   ; DATAIN[4] ; TEMP[4] ; CLK      ;
+-------+--------------+------------+-----------+---------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+---------+------------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To         ; From Clock ;
+-------+--------------+------------+---------+------------+------------+
; N/A   ; None         ; 8.627 ns   ; TEMP[4] ; DATAOUT[4] ; CLK        ;
; N/A   ; None         ; 8.384 ns   ; TEMP[1] ; DATAOUT[1] ; CLK        ;
; N/A   ; None         ; 8.254 ns   ; TEMP[7] ; DATAOUT[7] ; CLK        ;
; N/A   ; None         ; 8.234 ns   ; TEMP[5] ; DATAOUT[5] ; CLK        ;
; N/A   ; None         ; 7.826 ns   ; TEMP[6] ; DATAOUT[6] ; CLK        ;
; N/A   ; None         ; 7.806 ns   ; TEMP[0] ; DATAOUT[0] ; CLK        ;
; N/A   ; None         ; 7.803 ns   ; TEMP[3] ; DATAOUT[3] ; CLK        ;
; N/A   ; None         ; 7.157 ns   ; TEMP[2] ; DATAOUT[2] ; CLK        ;
+-------+--------------+------------+---------+------------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+-----------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To      ; To Clock ;
+---------------+-------------+-----------+-----------+---------+----------+
; N/A           ; None        ; -1.288 ns ; DATAIN[4] ; TEMP[4] ; CLK      ;
; N/A           ; None        ; -1.353 ns ; DATAIN[7] ; TEMP[7] ; CLK      ;
; N/A           ; None        ; -1.386 ns ; DATAIN[2] ; TEMP[2] ; CLK      ;
; N/A           ; None        ; -1.392 ns ; DATAIN[1] ; TEMP[1] ; CLK      ;
; N/A           ; None        ; -1.424 ns ; RIGHT     ; TEMP[7] ; CLK      ;
; N/A           ; None        ; -1.494 ns ; LEFT      ; TEMP[0] ; CLK      ;
; N/A           ; None        ; -1.727 ns ; DATAIN[0] ; TEMP[0] ; CLK      ;
; N/A           ; None        ; -1.737 ns ; MODE[1]   ; TEMP[7] ; CLK      ;
; N/A           ; None        ; -1.783 ns ; DATAIN[3] ; TEMP[3] ; CLK      ;
; N/A           ; None        ; -1.843 ns ; DATAIN[6] ; TEMP[6] ; CLK      ;
; N/A           ; None        ; -2.200 ns ; MODE[1]   ; TEMP[0] ; CLK      ;
; N/A           ; None        ; -2.200 ns ; MODE[1]   ; TEMP[2] ; CLK      ;
; N/A           ; None        ; -2.210 ns ; MODE[1]   ; TEMP[1] ; CLK      ;
; N/A           ; None        ; -2.211 ns ; MODE[1]   ; TEMP[4] ; CLK      ;
; N/A           ; None        ; -2.211 ns ; MODE[1]   ; TEMP[6] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[0] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[1] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[2] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[3] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[4] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[5] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[6] ; CLK      ;
; N/A           ; None        ; -2.269 ns ; MODE[0]   ; TEMP[7] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[0] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[1] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[2] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[3] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[4] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[5] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[6] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; RESET     ; TEMP[7] ; CLK      ;
; N/A           ; None        ; -2.472 ns ; MODE[1]   ; TEMP[3] ; CLK      ;
; N/A           ; None        ; -2.472 ns ; MODE[1]   ; TEMP[5] ; CLK      ;
; N/A           ; None        ; -2.610 ns ; DATAIN[5] ; TEMP[5] ; CLK      ;
+---------------+-------------+-----------+-----------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Dec 22 23:58:54 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off RL_SHIFT -c RL_SHIFT
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 304.04 MHz between source register "TEMP[2]" and destination register "TEMP[3]"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.198 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N8; Fanout = 3; REG Node = 'TEMP[2]'
            Info: 2: + IC(1.918 ns) + CELL(0.280 ns) = 2.198 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'TEMP[3]'
            Info: Total cell delay = 0.280 ns ( 12.74 % )
            Info: Total interconnect delay = 1.918 ns ( 87.26 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 3.681 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N9; Fanout = 3; REG Node = 'TEMP[3]'
                Info: Total cell delay = 2.081 ns ( 56.53 % )
                Info: Total interconnect delay = 1.600 ns ( 43.47 % )
            Info: - Longest clock path from clock "CLK" to source register is 3.681 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N8; Fanout = 3; REG Node = 'TEMP[2]'
                Info: Total cell delay = 2.081 ns ( 56.53 % )
                Info: Total interconnect delay = 1.600 ns ( 43.47 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "TEMP[0]" (data pin = "MODE[0]", clock pin = "CLK") is 3.536 ns
    Info: + Longest pin to register delay is 6.884 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_E4; Fanout = 9; PIN Node = 'MODE[0]'
        Info: 2: + IC(3.844 ns) + CELL(1.908 ns) = 6.884 ns; Loc. = LC_X1_Y7_N7; Fanout = 2; REG Node = 'TEMP[0]'
        Info: Total cell delay = 3.040 ns ( 44.16 % )
        Info: Total interconnect delay = 3.844 ns ( 55.84 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N7; Fanout = 2; REG Node = 'TEMP[0]'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
Info: tco from clock "CLK" to destination pin "DATAOUT[4]" through register "TEMP[4]" is 8.627 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP[4]'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.570 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP[4]'
        Info: 2: + IC(2.248 ns) + CELL(2.322 ns) = 4.570 ns; Loc. = PIN_G3; Fanout = 0; PIN Node = 'DATAOUT[4]'
        Info: Total cell delay = 2.322 ns ( 50.81 % )
        Info: Total interconnect delay = 2.248 ns ( 49.19 % )
Info: th for register "TEMP[4]" (data pin = "DATAIN[4]", clock pin = "CLK") is -1.288 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.681 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_H5; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP[4]'
        Info: Total cell delay = 2.081 ns ( 56.53 % )
        Info: Total interconnect delay = 1.600 ns ( 43.47 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.190 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_H2; Fanout = 1; PIN Node = 'DATAIN[4]'
        Info: 2: + IC(3.467 ns) + CELL(0.591 ns) = 5.190 ns; Loc. = LC_X1_Y7_N1; Fanout = 3; REG Node = 'TEMP[4]'
        Info: Total cell delay = 1.723 ns ( 33.20 % )
        Info: Total interconnect delay = 3.467 ns ( 66.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 22 23:58:55 2008
    Info: Elapsed time: 00:00:01