tb_atan.v

使用verilog语言完成了基于cordic算法求反正切的计算

`timescale 1ns/1ns
module TB_ATAN;
	parameter  DATA_WIDTH  = 11;
	parameter  ANGLE_WIDTH = 12;
	reg               aclr;
	reg   			 	    clk;
	reg   [DATA_WIDTH-1:0]   imag_in, real_in;
	wire  [ANGLE_WIDTH-1:0]  angle_out;
	
	initial
	    begin
	    	aclr = 1'b0;
	    	clk  = 1'b0;
	  #20 aclr = 1'b1;
	  #10 aclr = 1'b0;
	  #10 real_in = 11'b000_0000_0000; 
	      imag_in = 11'b111_1111_1110;
	  #20 real_in = 11'b000_0010_0100;
	      imag_in = 11'b000_0010_0100;
	  #20 real_in = 11'b111_1100_1011;
	      imag_in = 11'b000_0110_1110;
	  #20 real_in = 11'b111_0101_1101;
	      imag_in = 11'b111_0100_0110;
	  #20 real_in = 11'b000_0010_0111;
	      imag_in = 11'b111_1100_0110;
      end
      
	always 
	    begin
	    	#10 clk <= ~clk;
	    end
	    
	CORDIC_ATAN U_CORDIC_ATAN
	    ( .aclr      ( aclr        ),
	      .clk       ( clk         ),
	      .imag_in   ( imag_in     ),
	      .real_in   ( real_in     ),
	      .angle_out ( angle_out   ));
	    	  
	      
endmodule