h_adder.vhd

来自「这个源程序是关于全加器的」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS --ENTITY DIRECT
  PORT(A,B:IN STD_LOGIC;
       CO,SO:OUT STD_LOGIC);
END ENTITY H_ADDER;
ARCHITECTURE ART2 OF H_ADDER IS
  BEGIN
    SO<=(A OR B)AND(A NAND B);
    CO<=NOT(A NAND B);
END ARCHITECTURE ART2;