orm2.vhd

来自「这个源程序是关于全加器的」· VHDL 代码 · 共 11 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ORM2 IS
  PORT(A,B:IN STD_LOGIC;
         C:OUT STD_LOGIC);--YOU MUST ADD ";"AFTER "()"
END ENTITY ORM2;
ARCHITECTURE ART1 OF ORM2 IS
  BEGIN
    C<=A OR B;
END ARCHITECTURE ART1;