gen_tb

用于verlilog自动产生testbench的脚本 用法：gen_tb <yourfilename>

#!/usr/bin/perl
my $file=$ARGV[0];
die "syntax:: gen_tb file_name.v" if ($file eq "");
open(inF,$file) or dienice("$file open failed");
@data=<inF>;
close(inF);

$inout=-1;
foreach $i (@data) {
    if($inout==1 || $i=~m/\/\*/) {
        if($inout==-1) {
            if($i=~m/\*\//){
                $i=~ s/\/\*.*\*\///;
                $inout=-1;
            }
            else {
                $i=~s/\/\*.*$//;
                $inout=1;
            }
        }
        else {
            if($i=~m/\*\//){
                $i=~ s/^.*\*\///;
                $inout=-1;
            }
            else {
                $i=" ";
                $inout=1;
            }
        }
    }
    if($i=~m/\/\//){
        $i=~ s/\/\/.*//;
        $i=~ s/\t/    /g;
        $i=~ s/^\s*//;
    }
}

#initial counters
$lines=scalar(@data);
$line=0;
$modfound=-1;
@moduledata=@data;
@inputdata=@data;
@outputdata=@data;
#find 'module'
for ($line=0;$line<$lines;$line++) {
    if($data[$line]=~ m/module/) {
        $modfound = $line;
        $line=$lines; #break out of the loop
    }
}
#if do not find `module` , exit
if($modfound==-1) {
    print("Unabel to instantiate-no occurance of `module` left justfied in file.\n");
    exit;
}

#find port list
$prefound = -1;
for ($line=$modfound;$line<$lines;$line++) {
    $data[$line]=~ s/#\s*\x28//;
    if($data[$line]=~m/\x28/) {
        $prefound=$line;
        $data[$line]=~ s/.*\x28//;
        $line=$lines;
    }
}
if($prefound==-1) {
    print("Unabel to instantiate-no occurance of `(`after module keyword.\n");
    exit;
}

$postfound = -1;
for($line=$prefound; $line<$lines; $line++) {
    $data[$line]=~ s/\/\*.*\*\///; # /*xxx*/
    #following added for 2001..
    $data[$line]=~ s/\s*(input|output|inout|parameter)\s*//; 
    $data[$line]=~ s/\s*signed\s*//; 
    $data[$line]=~ s/\s*(reg|wire)\s*//; 
    $data[$line]=~ s/\s*\x5b.*\x5d\s*//; 

    while ($data[$line]=~m/\s*(\w[\w\d]*)/) { #find a port name 
        push(@ports,$1);
        $data[$line]=~ s/\s*\w[\w\d]*\s*,?//;
    }
    if($data[$line]=~ m/\s*\x29/) {
        $data[$line]=~ s/\s*\x29//;
        $postfound=$line;
        $line=$lines;
    }
}
#if can not find `)` 
if($postfound==-1) {
    print("Unabel to instantiate-no occurance of `)`after module keyword.\n");
    exit;
}
#Date MM/DD/YYYY
my $year    = 2000+ `date +%y`;
my $month   = `date +%m`;
my $day     = `date +%d`;
chomp($year);
chomp($month);
chomp($day);

my $author= $ENV{LOGNAME};

$file =~ s/.*\///g;
$file =~ s/\x2e.*//;
$wire = "wire";
for($inputline = 0; $inputline<$lines;$inputline++) {
    while($inputdata[$inputline] =~ m/\s*(input)(.*)/) {
        $tmp_input = $2;
        $tmp_input0 = $2;
        if($tmp_input =~ m/\[.*\]/) {
            $tmp_input =~ s/.*\[//;
            $tmp_input =~ s/\].*//;
            $tmp_input ="[".$tmp_input."]";
        }
        else {
            $tmp_input ="";
        }
        push (@inputs_width,$tmp_input);
        $tmp_input0 =~ s/\[.*\]//;
        $tmp_input0 =~ s/input//;
        $tmp_input0 =~ s/^\s*//;
        $tmp_input0 =~ s/;.*//;
        push (@inputs,$tmp_input0);
        $inputdata[$inputline] =~ s/\s*(input)(.*)//;
    }
}

for ($outputline = 0;$outputline < $lines; $outputline++) {
    while($outputdata[$outputline] =~ m/\s*(output)(.*)/) {
        $tmp_output = $2;
        $tmp_output0 = $2;
        if($tmp_output =~ m/\[.*\]/) {
            $tmp_output =~ s/.*\[//;
            $tmp_output =~ s/\].*//;
            $tmp_output ="[".$tmp_output."]";
        }
        else {
            $tmp_output ="";
        }
        push (@outputs_width,$tmp_output);
        $tmp_output0 =~ s/\[.*\]//;
        $tmp_output0 =~ s/output//;
        $tmp_output0 =~ s/^\s*//;
        $tmp_output0 =~ s/;.*//;
        push (@outputs,$tmp_output0);
        $outputdata[$outputline] =~ s/\s*(output)(.*)//;
    }

}

$lastport = $ports[scalar(@ports)-1];

for ($moduleline = 0;$moduleline < $lines; $moduleline++) {
    if($moduledata[$moduleline] =~ m/module\s+(\w+)\s*/) {
        $module = $1;
        $line = $lines;
    }
}
sub printline{
    ($n)=@_;
    if($n==1) { printf("//"."-"x 62 ."\n");}
    if($n==2) { printf("//--"."="x 58 ."--\n");}
    if($n==3) { printf("//--"."="x 27 ."end"."="x 28 ."--\n");}
}

printline 2;
printf("//Copyright(c) $year, Conexant system Inc. All rights Reserved\n");
printf("//Filename tb_$module.v\n");
printf("//Author $author\n");
printf("//Date $year-$month-$day\n");
printf("//Version 1.0\n");
printf("\n");
printline 2;
printf("\n");
printf("`timescale 1ns/1ns\n");
printf("\n");
printf("module tb_$module;\n");
printf("\n");
printline 1;
$ii=0;
foreach $j (@inputs) {
    if ($inputs_width[$ii] eq "") {
        printf("%-20s%-18s;\n",$wire,,$j);
    }
    else {
        printf("%-8s%-12s%-18s;\n",$wire,$inputs_width[$ii],$j);
    }
    $ii++;
}
printf("\n");

$ii=0;
foreach $l (@outputs) {
    if ($outputs_width[$ii] eq "") {
        printf("%-20s%-18s;\n",$wire,,$l);
    }
    else {
        printf("%-8s%-12s%-18s;\n",$wire,$outputs_width[$ii],$l);
    }
    $ii++;
}

printf("\n");
printline 1;

printf("$module u$module(");
foreach $i (@ports) {
    printf("\n                .%-20s(%-20s)",$i,$i);  #print the ports
    if ($i ne $lastport) {
        printf(",");
    }
}
printf("\n                );\n");
printf("\n");
printline 1;

printf("\n");
printf("endmodule\n");
printf("\n");
printline 1;
printline 3;
exit;
                
sub dienice {
    my($errmsg) =@_;
    print"$errmsg\n";
    exit
}