eccerrloc.vhd

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· VHDL 代码 · 共 146 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:58:15 04/15/2008 
-- Design Name: 
-- Module Name:    ECCErrLoc - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ECCErrLoc is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  ND : in STD_LOGIC;
			  eccValid : in STD_LOGIC;
           newECC : in  STD_LOGIC_VECTOR (23 downto 0);
           oldECC : in  STD_LOGIC_VECTOR (23 downto 0);
           DIN : in  STD_LOGIC_VECTOR (7 downto 0);
           Result : out  STD_LOGIC;--记录误码位置
           EnCorrect : out  STD_LOGIC;--表明有一个误码，可以纠错
           NeedInt : out  STD_LOGIC;--无法纠错
           DOUT : out  STD_LOGIC_VECTOR (7 downto 0));
end ECCErrLoc;

architecture Behavioral of ECCErrLoc is

signal EccXor : std_logic_vector(23 downto 0);

signal adjacency : std_logic_vector(10 downto 0);

signal EccLoc : std_logic_vector(10 downto 0);

signal newEcc_reg, oldEcc_reg : std_logic_vector(23 downto 0);
begin

LatchEccCode: process(clk,reset)--256个数的ECC码产生后，锁存新旧ECC码
begin
	if reset = '1' then
		newEcc_reg <= (others=> '0');
		oldEcc_reg <= (others=> '0');
	elsif (rising_edge(clk)) then
		if eccValid = '1' then
			newEcc_reg <= newEcc;
			oldEcc_reg <= oldEcc;
		end if;
	end if;
end process;

EccXor <= (newEcc_reg(23) xor oldEcc_reg(23)) & --新旧ECC码异或
          (newEcc_reg(22) xor oldEcc_reg(22)) & 
          (newEcc_reg(21) xor oldEcc_reg(21)) & 
          (newEcc_reg(20) xor oldEcc_reg(20)) & 
          (newEcc_reg(19) xor oldEcc_reg(19)) & 
          (newEcc_reg(18) xor oldEcc_reg(18)) & 
          (newEcc_reg(17) xor oldEcc_reg(17)) & 
          (newEcc_reg(16) xor oldEcc_reg(16)) & 
          (newEcc_reg(15) xor oldEcc_reg(15)) & 
          (newEcc_reg(14) xor oldEcc_reg(14)) & 
          (newEcc_reg(13) xor oldEcc_reg(13)) &
          (newEcc_reg(12) xor oldEcc_reg(12)) &
          (newEcc_reg(11) xor oldEcc_reg(11)) &
          (newEcc_reg(10) xor oldEcc_reg(10)) &
          (newEcc_reg(9) xor oldEcc_reg(9)) &
          (newEcc_reg(8) xor oldEcc_reg(8)) &
          (newEcc_reg(7) xor oldEcc_reg(7)) &
          (newEcc_reg(6) xor oldEcc_reg(6)) &
          (newEcc_reg(5) xor oldEcc_reg(5)) &
          (newEcc_reg(4) xor oldEcc_reg(4)) &
          (newEcc_reg(3) xor oldEcc_reg(3)) &
          (newEcc_reg(2) xor oldEcc_reg(2)) &
          0 & 0;
			 
adjacency <= (EccXor(2) xor EccXor(3)) & 
				 (EccXor(4) xor EccXor(5)) &
				 (EccXor(6) xor EccXor(7)) &
				 (EccXor(8) xor EccXor(9)) &
				 (EccXor(10) xor EccXor(11)) &
				 (EccXor(12) xor EccXor(13)) &
				 (EccXor(14) xor EccXor(15)) &
				 (EccXor(16) xor EccXor(17)) &
				 (EccXor(18) xor EccXor(19)) &
				 (EccXor(20) xor EccXor(21)) &
				 (EccXor(22) xor EccXor(23));--判定是否有误
				 
EccLoc <= EccXor(23) & EccXor(21) & EccXor(19) & 
			  EccXor(17) & EccXor(15) & EccXor(13) & 
			  EccXor(11) & EccXor(9) & EccXor(7) & 
			  EccXor(5) & EccXor(3);--取P1024H-P8H，P4H-P1H来确定误码位置
			  
ECCLocation: process(reset,clk)
begin
	if (reset = '1') then
		EnCorrect <= '0';
		NeedInt <= '0';
		Result <= (others => '0');
	elsif(rising_edge(clk)) then
		if adjacency = "00000000000" then--表明没有误码
			EnCorrent <= '0';
			NeedInt <= '0';
			Result <= (others => '0');
		elsif adjacency = "11111111111" then--表明有一个误码，可以纠错
			EnCorrent <= '1';
			NeedInt <= '0';
			Result <= EccLoc;
		else--无法纠正误码
			EnCorrent <= '0';
			NeedInt <= '1';
			Result <= EccLoc;
		end if;
	end if;
end process;

OutputData: process(clk,Reset)
begin
	if reset = '1' then
		DOUT <= (others=> '0');
	elsif (rising_edge(clk)) then
		if ND = '1' then
			DOUT <= DIN;
		end if;
	end if;
end process;
			

end Behavioral;