eccgen256byte.vhd

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· VHDL 代码 · 共 264 行

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Zhuo Zhihai
-- 
-- Create Date:    17:30:28 04/06/2008 
-- Design Name: 
-- Module Name:    eccGen256byte - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eccGen256byte is
    Port ( reset : in  STD_LOGIC;	--active high
           clk : in  STD_LOGIC;
           data : in  STD_LOGIC_VECTOR (7 downto 0);	-- input data for ecc calculate
			  ND		: in STD_LOGIC;	-- new data input for ecc calculate
			  WR_EN : in STD_LOGIC;
           eccValid : out  STD_LOGIC;	-- acitve high, indicate eccCode is valid
           eccCode : out  STD_LOGIC_VECTOR (23 downto 0));	-- ecc code output
end eccGen256byte;

architecture Behavioral of eccGen256byte is

component eccTab256
	port (
	a: IN std_logic_VECTOR(7 downto 0);
	clk: IN std_logic;
	qspo: OUT std_logic_VECTOR(7 downto 0));
END component;

component FIFO8x16
	port (
	DIN : IN std_logic_vector(7 downto 0);
	WR_EN : IN std_logic;
	RD_EN : IN std_logic;
	clk : IN std_logic;
	rst : IN std_logic;
	DOUT : out std_logic_vector(7 downto 0);
	FULL : out std_logic;
	Empty : out std_logic);
end component;

signal P8H,P8L		: std_logic;	-- P8 P8'
signal P16H,P16L	: std_logic;	-- P16 P16'
signal P32H,P32L	: std_logic;	-- P32 P32'
signal P64H,P64L	: std_logic;	-- P64 P64'
signal P128H,P128L: std_logic;	-- P128 P128'
signal P256H,P256L: std_logic;	-- P256 P256'
signal P512H,P512L: std_logic;	-- P512 P512'
signal P1024H,P1024L	: std_logic;-- P1024 P1024'
signal eccTab_dout	: std_logic_vector(7 downto 0);

signal eccCode_3	: std_logic_vector(7 downto 0);	-- ecc code byte 3

signal dataCount	: std_logic_vector(7 downto 0);

signal eccValid_pre	: std_logic;

signal CNT : std_logic;

signal start : std_logic;

signal datatmp : std_logic_vector(7 downto 0);

signal RD_tmp : std_logic;

signal Empty : std_logic;

--signal clknot : std_logic;
begin


--clknot <= not clk;
eccCode(7 downto 0) <= eccCode_3;
eccCode(23 downto 16) <= P64H & P64L & p32H & P32L & p16H & P16L & p8H & P8L;
eccCode(15 downto 8)  <= P1024H & P1024L & P512H & P512L & p256H & P256L & p128H & P128L;

inst_eccTab: eccTab256
	port map(
	a	=>	datatmp,
	clk=> clk,
	qspo=> eccTab_dout);
	
inst_FIFO: FIFO8x16
	port map(
	DIN => data,
	WR_EN => WR_EN,
	RD_EN => RD_tmp,
	clk => clk,
	rst => reset,
	DOUT => datatmp,
	FULL => open,
	EMPTY => Empty);	
	
process(reset,clk)
begin
	if reset = '1' then
		dataCount <= (others => '0');
	elsif clk'event and clk = '1' then
		if CNT = '1' then
			dataCount <= dataCount + '1';
		else
			dataCount <= x"00";
		end if;
	end if;
end process;

--- generate eccCode
process(reset,clk)
begin
	if reset = '1' then
	
		P8H 	<= '0';P8L <= '0';
		P16H 	<= '0';P16L <= '0';
		P32H 	<= '0';P32L <= '0';
		P64H 	<= '0';P64L <= '0';
		P128H <= '0';P128L <= '0';
		P256H <= '0';P256L <= '0';
		P512H <= '0';P512L <= '0';
		P1024H <= '0';P1024L <= '0';
		eccCode_3 <= (1=> '1',0 =>'1',others =>'0');

		eccValid<= '0';

		eccValid_pre <= '0';
		
	elsif clk'event and clk ='1' then

		if dataCount = x"FE" then

			eccValid_pre <= '1';

		else 

			eccValid_pre <= '0';

		end if;

		eccValid	<= eccValid_pre;

		if dataCount = x"00" and start = '0' then

			P8H 	<= '0';P8L <= '0';
			P16H 	<= '0';P16L <= '0';
			P32H 	<= '0';P32L <= '0';
			P64H 	<= '0';P64L <= '0';
			P128H <= '0';P128L <= '0';
			P256H <= '0';P256L <= '0';
			P512H <= '0';P512L <= '0';
			P1024H <= '0';P1024L <= '0';
			eccCode_3 <=(1=> '1',0 =>'1',others =>'0');	
		elsif start = '1' then
			eccCode_3(7 downto 2) <= eccCode_3(7 downto 2) xor eccTab_dout(5 downto 0);
			if dataCount(0) = '1' then
				P8H <= P8H xor eccTab_dout(6);	--P8
			else
				P8L <= P8L xor eccTab_dout(6); --P8'
			end if;
			
			if dataCount(1) ='1' then
				P16H <= P16H xor eccTab_dout(6);
			else
				P16L <= P16L xor eccTab_dout(6);
			end if;
    	
			if dataCount(2) ='1'then
				P32H <= P32H xor eccTab_dout(6);
			else
				P32L <= P32L xor eccTab_dout(6);
			end if;	
			
			if dataCount(3) ='1'then
				P64H <= P64H xor eccTab_dout(6);
			else
				P64L <= P64L xor eccTab_dout(6);
			end if;	
			
			if dataCount(4) ='1'then
				P128H <= P128H xor eccTab_dout(6);
			else
				P128L <= P128L xor eccTab_dout(6);
			end if;	
			
			if dataCount(5) ='1'then
				P256H <= P256H xor eccTab_dout(6);
			else
				P256L <= P256L xor eccTab_dout(6);
			end if;	
			
			if dataCount(6) ='1'then
				P512H <= P512H xor eccTab_dout(6);
			else
				P512L <= P512L xor eccTab_dout(6);
			end if;
			
			if dataCount(7) ='1'then
				P1024H <= P1024H xor eccTab_dout(6);
			else
				P1024L <= P1024L xor eccTab_dout(6);
			end if;
		end if;
	end if;
end process;

statemachine: process(clk,reset)
variable Cstate : integer range 0 to 2;
begin
	if (reset = '1') then
		Cstate := 0;
		start <= '0';
		RD_tmp <= '0';
		CNT <= '0';
	elsif(rising_edge(clk)) then
		case Cstate is
		when 0 =>
			if ND='1' and Empty = '0' then
				Cstate := 1;
				start <= '1';
				RD_tmp <= '1';
			else
				Cstate := 0;
				start <= '0';
			end if;
		when 1 =>
			if dataCount = x"FF" then
				Cstate := 2;
			else
				Cstate := 1;
			end if;	
			
			if dataCount = x"FE" then
				RD_tmp <= '0';
			end if;
			start <= '1';
		when others =>
			Cstate :=0;
			start <= '0';
			RD_tmp <= '0';
		end case;
		CNT <= RD_tmp;
	end if;
end process;	

end Behavioral;