coregen.xml

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· XML 代码 · 共 143 行

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="rom256byte" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
rom256byte YourInstanceName (
    .a(a), // Bus [7 : 0] 
    .clk(clk),
    .qspo(qspo)); // Bus [7 : 0] 

 
		</Template>
		<Template label="eccTab256" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
eccTab256 YourInstanceName (
    .a(a), // Bus [7 : 0] 
    .clk(clk),
    .qspo(qspo)); // Bus [7 : 0] 

 
		</Template>
		<Template label="FIFO8x16" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
FIFO8x16 YourInstanceName (
    .clk(clk),
    .din(din), // Bus [7 : 0] 
    .rd_en(rd_en),
    .rst(rst),
    .wr_en(wr_en),
    .dout(dout), // Bus [7 : 0] 
    .empty(empty),
    .full(full));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="rom256byte" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component rom256byte
    port (
    a: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    qspo: OUT std_logic_VECTOR(7 downto 0));
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : rom256byte
        port map (
            a =&gt; a,
            clk =&gt; clk,
            qspo =&gt; qspo);
 
		</Template>
		<Template label="eccTab256" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component eccTab256
    port (
    a: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    qspo: OUT std_logic_VECTOR(7 downto 0));
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : eccTab256
        port map (
            a =&gt; a,
            clk =&gt; clk,
            qspo =&gt; qspo);
 
		</Template>
		<Template label="FIFO8x16" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component FIFO8x16
    port (
    clk: IN std_logic;
    din: IN std_logic_VECTOR(7 downto 0);
    rd_en: IN std_logic;
    rst: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;


 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : FIFO8x16
        port map (
            clk =&gt; clk,
            din =&gt; din,
            rd_en =&gt; rd_en,
            rst =&gt; rst,
            wr_en =&gt; wr_en,
            dout =&gt; dout,
            empty =&gt; empty,
            full =&gt; full);
 
		</Template>
	</Folder>
</RootFolder>