eccgen256byte.vif

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· VIF 代码 · 共 58 行

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  eccGen256byte.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Xilinx

# RTL and technology files
vif_add_file -original -vhdl -lib work ./eccTab256.vhd
vif_add_file -original -vhdl -lib work ./eccGen256byte.vhd
vif_set_top_module -original -top eccGen256byte
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog eccGen256byte.vm
vif_set_top_module -translated -top eccGen256byte 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies
vif_set_equiv -translated dataCount_Z[2] dataCount_fast_Z[2]
vif_set_equiv -translated dataCount_Z[1] dataCount_fast_Z[1]
vif_set_equiv -translated dataCount_Z[0] dataCount_fast_Z[0]

# Inversion map points

# Port mappping and directions

# Black box mapping
vif_set_black_box eccTab256

vif_set_map_point -blackbox -original inst_eccTab -translated inst_eccTab

# Other sequential cells, including multidimensional arrays

# Constant Registers

# Retimed Registers