tb_ecc.vhd

基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序

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-- Company: 
-- Engineer:
--
-- Create Date:   10:19:50 04/13/2008
-- Design Name:   eccGen256byte
-- Module Name:   D:/work/eccGen256byte/tb_ecc.vhd
-- Project Name:  eccGen256byte
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: eccGen256byte
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_ecc_vhd IS
END tb_ecc_vhd;

ARCHITECTURE behavior OF tb_ecc_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT eccGen256byte
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		data : IN std_logic_vector(7 downto 0);
		ND : IN std_logic;  
		WR_EN : in STD_LOGIC;
		eccValid : OUT std_logic;
		eccCode : OUT std_logic_vector(23 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL ND :  std_logic := '0';
	SIGNAL data :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL WR_EN : std_logic := '0';

	--Outputs
	SIGNAL eccValid :  std_logic;
	SIGNAL eccCode :  std_logic_vector(23 downto 0);
	constant clk_period : time := 33 ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: eccGen256byte PORT MAP(
		reset => reset,
		clk => clk,
		data => data,
		ND => ND,
		WR_EN => WR_EN,
		eccValid => eccValid,
		eccCode => eccCode
	);
	
	clk_gen : process
	begin
		clk <= '1';
		wait for clk_period/2;
		clk <= '0';
		wait for clk_period/2;
	end process;

	tb : PROCESS
	variable i : integer range 0 to 2048;
	BEGIN
		wait for clk_period;
		Reset <= '1';
		wait for clk_period;
		Reset <= '0';
		WR_EN <= '1';
		wait for clk_period;
		ND <= '1';
--		wait for clk_period;
--		data <= data + '1';
		i := 0;
		while (i<2048) loop
		wait for clk_period;
		data <= data + '1';
		i := i+1;
		end loop;
--		wait for clk_period;
--		data <= x"00";
--		wait for 2*clk_period;
--		i := 0;
--		while (i<256) loop
--		wait for clk_period;
--		data <= data + '1';
--		i := i+1;
--		end loop;
--		-- Wait 100 ns for global reset to finish
--		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;