fifo8x16.xco

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· XCO 代码 · 共 78 行

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#
# Xilinx Core Generator version J.36
# Date: Mon Apr 14 14:07:23 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2vp30
SET devicefamily = virtex2p
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1152
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -7
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 3.3
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=FIFO8x16
CSET data_count=false
CSET data_count_width=4
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET fifo_implementation=Common_Clock_Distributed_RAM
CSET full_threshold_assert_value=14
CSET full_threshold_negate_value=13
CSET input_data_width=8
CSET input_depth=16
CSET output_data_width=8
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=100
CSET read_data_count=false
CSET read_data_count_width=4
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=100
CSET write_data_count=false
CSET write_data_count_width=4
# END Parameters
GENERATE
# CRC: e729a361