📄 eccgen256byte.vhd.bak
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------------------------------------------------------------------------------------ Company: -- Engineer: Zhuo Zhihai-- -- Create Date: 17:30:28 04/06/2008 -- Design Name: -- Module Name: eccGen256byte - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity eccGen256byte is Port ( reset : in STD_LOGIC; --active high clk : in STD_LOGIC; data : in STD_LOGIC_VECTOR (7 downto 0); ND : in STD_LOGIC; -- new data input for ecc calculate eccValid : out STD_LOGIC; eccCode : out STD_LOGIC_VECTOR (23 downto 0));end eccGen256byte;architecture Behavioral of eccGen256byte iscomponent eccTab256 port ( a: IN std_logic_VECTOR(7 downto 0); clk: IN std_logic; qspo: OUT std_logic_VECTOR(7 downto 0));END component;signal P8H,P8L : std_logic; -- P8 P8'signal P16H,P16L : std_logic; -- P16 P16'signal P32H,P32L : std_logic; -- P32 P32'signal P64H,P64L : std_logic; -- P64 P64'signal P128H,P128L: std_logic; -- P128 P128'signal P256H,P256L: std_logic; -- P256 P256'signal P512H,P512L: std_logic; -- P512 P512'signal P1024H,P1024L : std_logic;-- P1024 P1024'signal eccTab_dout : std_logic_vector(7 downto 0);signal eccCode_3 : std_logic_vector(7 downto 0); -- ecc code byte 3signal dataCount : std_logic_vector(7 downto 0);signal eccValid_pre : std_logic;begineccCode(7 downto 0) <= eccCode_3;eccCode(23 downto 16) <= P64H & P64L & p32H & P32L & p16H & P16L & p8H & P8L;eccCode(15 downto 8) <= P1024H & P1024L & P512H & P512L & p256H & P256L & p128H & P128L;inst_eccTab: eccTab256 port map( a => data, clk=> clk, qspo=> eccTab_dout); process(reset,clk)begin if reset = '1' then dataCount <= (others => '0'); elsif clk'event and clk = '1' then if ND = '1' then dataCount <= dataCount + '1'; end if; end if;end process;--- generate eccCodeprocess(reset,clk)begin if reset = '1' then P8H <= '0';P8L <= '0'; P16H <= '0';P16L <= '0'; P32H <= '0';P32L <= '0'; P64H <= '0';P64L <= '0'; P128H <= '0';P128L <= '0'; P256H <= '0';P256L <= '0'; P512H <= '0';P512L <= '0'; P1024H <= '0';P1024L <= '0'; eccCode_3 <= (1=> '1',0 =>'1',others =>'0'); eccValid<= '0'; eccValid_pre <= '0'; elsif clk'event and clk ='1' then if dataCount = x"FF" then eccValid_pre <= '1'; else eccValid_pre <= '0'; end if; eccValid <= eccValid_pre; if dataCount = x"00" and ND = '0' hen P8H <= '0';P8L <= '0'; P16H <= '0';P16L <= '0'; P32H <= '0';P32L <= '0'; P64H <= '0';P64L <= '0'; P128H <= '0';P128L <= '0'; P256H <= '0';P256L <= '0'; P512H <= '0';P512L <= '0'; P1024H <= '0';P1024L <= '0'; eccCode_3 <= (others =>'0'); end if; if ND = '1' then eccCode_3 <= eccCode_3 xor eccTab_dout; if dataCount(0) = '1' then P8H<= P8H xor eccTab_dout(7); --P8 else P8L<= P8L xor eccTab_dout(7); --P8' end if; if dataCount(1) ='1' then P16H <= P16H xor eccTab_dout(7); else P16L <= P16L xor eccTab_dout(7); end if; if dataCount(2) ='1'then P32H <= P32H xor eccTab_dout(7); else P32L <= P32L xor eccTab_dout(7); end if; if dataCount(3) ='1'then P64H <= P64H xor eccTab_dout(7); else P64L <= P64L xor eccTab_dout(7); end if; if dataCount(4) ='1'then P128H <= P128H xor eccTab_dout(7); else P128L <= P128L xor eccTab_dout(7); end if; if dataCount(5) ='1'then P256H <= P256H xor eccTab_dout(7); else P256L <= P256L xor eccTab_dout(7); end if; if dataCount(6) ='1'then P512H <= P512H xor eccTab_dout(7); else P512L <= P512L xor eccTab_dout(7); end if; if dataCount(7) ='1'then P1024H <= P1024H xor eccTab_dout(7); else P1024L <= P1024L xor eccTab_dout(7); end if; end if;end process;end Behavioral;
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