layer0.tlg

来自「基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,」· TLG 代码 · 共 6 行

@N: CD630 :"D:\work1\eccGen256byte\eccGen256byte.vhd":30:7:30:19|Synthesizing work.eccgen256byte.behavioral 
@N: CD630 :"D:\work1\eccGen256byte\eccTab256.vhd":43:7:43:15|Synthesizing work.ecctab256.ecctab256_a 
@W: CD286 :"D:\work1\eccGen256byte\eccTab256.vhd":43:7:43:15|Creating black box for empty architecture eccTab256 
Post processing for work.ecctab256.ecctab256_a
Post processing for work.eccgen256byte.behavioral