📄 maichong.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity maichong is
port (D:in std_logic_vector(0 to 7);
load:in std_logic;
clk:in std_logic;
pout:buffer std_logic;
test:out std_logic;
dis,lcd,lcdcontrol:out std_logic_vector(0 to 7)
);
end maichong;
architecture rtl of maichong is
--component fenpin
-- PORT (clk:IN std_logic;
-- clk2:BUFFER std_logic );
--end component;
signal control,clk2 : std_logic;
signal pcount:std_logic_vector(0 to 7);
begin
--u1: fenpin PORT MAP(clk,clk2);
process(clk,LOAD) --减数模块,当count不为0时使contorl=1
variable count:std_logic_vector(0 to 7) :="00000000";
begin
if load='1' then
count:=D; --异步置数
else if (clk'event and clk='1') then
if count /=0 then
count:=count-1;
end if;
IF count>0 THEN
control<='1';
else
control<='0';
end if;
end if;
end if;
end process;
process(clk,control) --脉冲,control=1时使pout=clk
begin
--pout<='0';
if control ='1' then
pout<=clk; -- pout<=clk;-其他任何地方用clk都改为clk的2或4分频,做个分频电路
else
pout<='0';
end if;
end process;
process(pout) --脉冲计数模块,将记录到的总脉冲数更新到pcount中
begin
if (pout'event and pout='1') then
pcount<=pcount+1;
end if ;
end process;
process(pcount) --显示模块,将pcount的值翻译为LCD码
begin
dis<=pcount;
case pcount is
WHEN "00000000" => lcd <= "11111100" ;--0
WHEN "00000001" => lcd <= "01100000" ;--1
WHEN "00000010" => lcd <= "11011010" ;--2
WHEN "00000011" => lcd <= "11110010" ;--3
WHEN "00000100" => lcd <= "01100110" ;--4
WHEN "00000101" => lcd <= "10110110" ;--5
WHEN "00000110" => lcd <= "10111110" ;--6
WHEN "00000111" => lcd <= "11100000" ;--7
WHEN "00001000" => lcd <= "11111110" ;--8
WHEN "00001001" => lcd <= "11110110" ;--9
WHEN OTHERS => lcd <= "11111100";
end case;
end process;
process(control) --测试
begin
test<=control;
end process;
lcdcontrol<="00000001";--前八位片选,最后一位设置小数点
end rtl;
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