null_pair_example.vhd

DDR2 Controller DDR2 Controller

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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 1.0
--  \   \         Application : NULL MGT Tile 
--  /   /         Filename : NULL_pair_example.vhd
-- /___/   /\     Date : 10/07/2005
-- \   \  /  \ 
--  \___\/\___\ 
-- 
-- 
--   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
--                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
--                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
--                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--                APPLICATION OR STANDARD, XILINX IS MAKING NO
--                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
--                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
--                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
--                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
--                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
--                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
--                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
--                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--                PURPOSE.
--
--                (c) Copyright 2004 Xilinx, Inc.
--                All rights reserved.
-- 

library IEEE;
use IEEE.std_logic_1164.all;


entity null_pair_example is
port
(
  clk        : in std_logic;
  rx1n       : in std_logic_vector(1 downto 0);
  rx1p       : in std_logic_vector(1 downto 0);
  tx1n       : out std_logic_vector(1 downto 0);
  tx1p       : out std_logic_vector(1 downto 0)
 );


end null_pair_example;

architecture structure of null_pair_example is

   
  -------------------------------------------------------------------
  --
  --  NULL_PAIR core component declaration
  --
  -------------------------------------------------------------------
   COMPONENT NULL_PAIR
      PORT (
        GREFCLK_IN              : IN std_logic;   
        RX1N_IN                 : IN std_logic_vector(1 DOWNTO 0);   
        RX1P_IN                 : IN std_logic_vector(1 DOWNTO 0);   
        TX1N_OUT                : OUT std_logic_vector(1 DOWNTO 0);   
        TX1P_OUT                : OUT std_logic_vector(1 DOWNTO 0));   
   END COMPONENT;

attribute box_type: string;
attribute box_type of NULL_PAIR: component is "user_black_box";

--   COMPONENT BUFG
--     PORT (
--        I                       : IN std_logic;
--        O                       : OUT std_logic);
--     END COMPONENT;

  -------------------------------------------------------------------
  --
  --  NULL_PAIR core signal declarations
  --
  -------------------------------------------------------------------

   signal global_sig : std_logic;


begin
           
  -------------------------------------------------------------------
  --
  --  GREFCLK_IN port needs to be driven with any global signal
  --  (any BUFG output, even a BUFG with ground for input will work).
  --
  -------------------------------------------------------------------
--           global_bufg_inst : BUFG
--           port map
--           (
--              I => clk,
--              O => global_sig
--           );
  
  global_sig <= clk;

  -------------------------------------------------------------------
  --
  --  NULL_PAIR core instance
  --
  -------------------------------------------------------------------
            null_pair_inst: NULL_PAIR
            port map
            (  
               GREFCLK_IN => global_sig,
               RX1N_IN    => rx1n,
               RX1P_IN    => rx1p,
               TX1N_OUT   => tx1n, 
               TX1P_OUT   => tx1p
            );


end structure;