watch.tan.qmsg

可以实现时间调节

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "minute:u4\|count\[5\] minute:u4\|count\[5\] en 1.2 ns " "Info: Found hold time violation between source pin or register minute:u4\|count\[5\] and destination pin or register minute:u4\|count\[5\] for clock en (Hold time is 1.2 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.300 ns + Largest " "Info: + Largest clock skew is 8.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en destination 21.100 ns + Longest register " "Info: + Longest clock path from clock en to destination register is 21.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en 1 CLK Pin_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_6; Fanout = 2; CLK Node = 'en'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { en } "NODE_NAME" } } } { "E:/vdhl试验/watch/watch.vhd" "" "" { Text "E:/vdhl试验/watch/watch.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(2.300 ns) 9.300 ns second:u3\|i33~3 2 COMB LC1_C7 8 " "Info: 2: + IC(3.500 ns) + CELL(2.300 ns) = 9.300 ns; Loc. = LC1_C7; Fanout = 8; COMB Node = 'second:u3\|i33~3'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.800 ns" { en second:u3|i33~3 } "NODE_NAME" } } } { "E:/vdhl试验/watch/second.vhd" "" "" { Text "E:/vdhl试验/watch/second.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 14.900 ns second:u3\|enmin~reg0 3 REG LC3_A17 2 " "Info: 3: + IC(4.500 ns) + CELL(1.100 ns) = 14.900 ns; Loc. = LC3_A17; Fanout = 2; REG Node = 'second:u3\|enmin~reg0'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.600 ns" { second:u3|i33~3 second:u3|enmin~reg0 } "NODE_NAME" } } } { "E:/vdhl试验/watch/second.vhd" "" "" { Text "E:/vdhl试验/watch/second.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.800 ns minute:u4\|i15~3 4 COMB LC4_A17 7 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 17.800 ns; Loc. = LC4_A17; Fanout = 7; COMB Node = 'minute:u4\|i15~3'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { second:u3|enmin~reg0 minute:u4|i15~3 } "NODE_NAME" } } } { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 21.100 ns minute:u4\|count\[5\] 5 REG LC8_A4 7 " "Info: 5: + IC(3.300 ns) + CELL(0.000 ns) = 21.100 ns; Loc. = LC8_A4; Fanout = 7; REG Node = 'minute:u4\|count\[5\]'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.300 ns" { minute:u4|i15~3 minute:u4|count[5] } "NODE_NAME" } } } { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns 43.60 % " "Info: Total cell delay = 9.200 ns ( 43.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.900 ns 56.40 % " "Info: Total interconnect delay = 11.900 ns ( 56.40 % )" {  } {  } 0}  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "21.100 ns" { en second:u3|i33~3 second:u3|enmin~reg0 minute:u4|i15~3 minute:u4|count[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en source 12.800 ns - Shortest register " "Info: - Shortest clock path from clock en to source register is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en 1 CLK Pin_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_6; Fanout = 2; CLK Node = 'en'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { en } "NODE_NAME" } } } { "E:/vdhl试验/watch/watch.vhd" "" "" { Text "E:/vdhl试验/watch/watch.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns minute:u4\|i15~3 2 COMB LC4_A17 7 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC4_A17; Fanout = 7; COMB Node = 'minute:u4\|i15~3'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "6.000 ns" { en minute:u4|i15~3 } "NODE_NAME" } } } { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 12.800 ns minute:u4\|count\[5\] 3 REG LC8_A4 7 " "Info: 3: + IC(3.300 ns) + CELL(0.000 ns) = 12.800 ns; Loc. = LC8_A4; Fanout = 7; REG Node = 'minute:u4\|count\[5\]'" {  } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.300 ns" { minute:u4|i15~3 minute:u4|count[5] } "NODE_NAME" } } } { "E:/vdhl试验/watch/minute.vhd" "" "" { Text "E:/vdhl试验/watch/minute.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 45.31 % " "Info: Total cell delay = 5.800 ns ( 45.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns 54.69 % " "Info: Total interconnect delay = 7.000 ns ( 54.69 % )" {  } {  } 0}  } { {