watch.map.eqn

可以实现时间调节

--F1L53 is act:u5|i84~528
--operation mode is normal

F1L53 = C1_count[4] & (F1L12 # D1L32 & !F1L46) # !C1_count[4] & D1L32 & !F1L46;


--F1L63 is act:u5|i84~530
--operation mode is normal

F1L63 = (!F1L53 & (!F1L43 # !F1L91) # !F1L32) & CASCADE(F1L33);


--M6_cs_buffer[3] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M6_cs_buffer[3] = C1_count[3] $ M6_cout[2];

--M6_cout[3] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M6_cout[3] = CARRY(C1_count[3] & M6_cout[2]);


--K9_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[6]
--operation mode is normal

K9_unreg_res_node[6] = M72_cout[5] $ E1_count[6];


--K8_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|unreg_res_node[6]
--operation mode is normal

K8_unreg_res_node[6] = M42_cout[5] $ E1_count[6];


--D1L04 is second:u3|i74~96
--operation mode is normal

D1L04 = D1L44 & (K5_unreg_res_node[6] # D1L24 & K3_unreg_res_node[6]) # !D1L44 & D1L24 & K3_unreg_res_node[6];


--M9_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M9_cs_buffer[5] = D1_count[5] $ M9_cout[4];

--M9_cout[5] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M9_cout[5] = CARRY(D1_count[5] & M9_cout[4]);


--M51_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M51_cs_buffer[5] = D1_count[5] $ M51_cout[4];

--M51_cout[5] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M51_cout[5] = CARRY(D1_count[5] & M51_cout[4]);


--D1L14 is second:u3|i75~96
--operation mode is normal

D1L14 = D1L44 & (M51_cs_buffer[5] # D1L24 & M9_cs_buffer[5]) # !D1L44 & D1L24 & M9_cs_buffer[5];


--C1_count[0] is msecond:u2|count[0]
--operation mode is normal

C1_count[0]_lut_out = C1L61 & !M6_cs_buffer[0];
C1_count[0] = DFFEA(C1_count[0]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--M6_cs_buffer[2] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M6_cs_buffer[2] = C1_count[2] $ M6_cout[1];

--M6_cout[2] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M6_cout[2] = CARRY(C1_count[2] & M6_cout[1]);


--M6_cs_buffer[1] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M6_cs_buffer[1] = C1_count[1] $ M6_cout[0];

--M6_cout[1] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M6_cout[1] = CARRY(C1_count[1] & M6_cout[0]);


--E1L72 is minute:u4|i25~0
--operation mode is normal

E1L72 = E1_clkhour[5] & (E1L72 # set_clk) # !E1_clkhour[5] & E1L72 & !set_clk;


--D1L62 is second:u3|i12~0
--operation mode is normal

D1L62 = D1_clkmin[5] & (D1L62 # set_clk) # !D1_clkmin[5] & D1L62 & !set_clk;


--D1L42 is second:u3|i11~0
--operation mode is normal

D1L42 = D1_clkmin[6] & (D1L42 # set_clk) # !D1_clkmin[6] & D1L42 & !set_clk;


--E1L52 is minute:u4|i24~0
--operation mode is normal

E1L52 = E1_clkhour[6] & (E1L52 # set_clk) # !E1_clkhour[6] & E1L52 & !set_clk;


--K3_unreg_res_node[6] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|unreg_res_node[6]
--operation mode is normal

K3_unreg_res_node[6] = M9_cout[5] $ D1_count[6];


--K5_unreg_res_node[6] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|unreg_res_node[6]
--operation mode is normal

K5_unreg_res_node[6] = M51_cout[5] $ D1_count[6];


--C1L21 is msecond:u2|i47~97
--operation mode is normal

C1L21 = C1L81 & (!C1_count[4] & !C1_count[5] # !C1_count[6]);


--M3_cs_buffer[4] is msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M3_cs_buffer[4] = C1_count[4] $ M3_cout[3];

--M3_cout[4] is msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M3_cout[4] = CARRY(C1_count[4] & M3_cout[3]);


--M6_cs_buffer[4] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M6_cs_buffer[4] = C1_count[4] $ M6_cout[3];

--M6_cout[4] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M6_cout[4] = CARRY(C1_count[4] & M6_cout[3]);


--C1L51 is msecond:u2|i49~96
--operation mode is normal

C1L51 = C1L61 & (M6_cs_buffer[4] # C1L21 & M3_cs_buffer[4]) # !C1L61 & C1L21 & M3_cs_buffer[4];


--C1L31 is msecond:u2|i47~98
--operation mode is normal

C1L31 = C1L61 & (K2_unreg_res_node[6] # K1_unreg_res_node[6] & C1L21) # !C1L61 & K1_unreg_res_node[6] & C1L21;


--M6_cs_buffer[0] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

M6_cs_buffer[0] = C1_count[0];

--M6_cout[0] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

M6_cout[0] = CARRY(C1_count[0]);


--M3_cs_buffer[5] is msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M3_cs_buffer[5] = C1_count[5] $ M3_cout[4];

--M3_cout[5] is msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M3_cout[5] = CARRY(C1_count[5] & M3_cout[4]);


--M6_cs_buffer[5] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M6_cs_buffer[5] = C1_count[5] $ M6_cout[4];

--M6_cout[5] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M6_cout[5] = CARRY(C1_count[5] & M6_cout[4]);


--C1L41 is msecond:u2|i48~96
--operation mode is normal

C1L41 = C1L61 & (M6_cs_buffer[5] # C1L21 & M3_cs_buffer[5]) # !C1L61 & C1L21 & M3_cs_buffer[5];


--B1L6 is any_even:u1|i~327
--operation mode is normal

B1L6 = H1_q[11] & H1_q[9] & H1_q[8] & !H1_q[10];


--B1L8 is any_even:u1|i~331
--operation mode is normal

B1L8 = (H1_q[14] & !H1_q[15] & !H1_q[13] & !H1_q[12]) & CASCADE(B1L6);


--B1L7 is any_even:u1|i~329
--operation mode is normal

B1L7 = H1_q[3] & H1_q[2] & H1_q[1] & !H1_q[0];


--B1L9 is any_even:u1|i~332
--operation mode is normal

B1L9 = (H1_q[5] & H1_q[4] & !H1_q[7] & !H1_q[6]) & CASCADE(B1L7);


--M21_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M21_cs_buffer[5] = D1_clkmin[5] $ M21_cout[4];

--M21_cout[5] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M21_cout[5] = CARRY(D1_clkmin[5] & M21_cout[4]);


--M81_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M81_cs_buffer[5] = D1_clkmin[5] $ M81_cout[4];

--M81_cout[5] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M81_cout[5] = CARRY(D1_clkmin[5] & M81_cout[4]);


--D1L64 is second:u3|i123~96
--operation mode is normal

D1L64 = D1L94 & (M81_cs_buffer[5] # D1L74 & M21_cs_buffer[5]) # !D1L94 & D1L74 & M21_cs_buffer[5];


--D1L54 is second:u3|i122~96
--operation mode is normal

D1L54 = D1L94 & (K6_unreg_res_node[6] # D1L74 & K4_unreg_res_node[6]) # !D1L94 & D1L74 & K4_unreg_res_node[6];


--M12_cs_buffer[5] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M12_cs_buffer[5] = E1_clkhour[5] $ M12_cout[4];

--M12_cout[5] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M12_cout[5] = CARRY(E1_clkhour[5] & M12_cout[4]);


--M03_cs_buffer[5] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M03_cs_buffer[5] = E1_clkhour[5] $ M03_cout[4];

--M03_cout[5] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M03_cout[5] = CARRY(E1_clkhour[5] & M03_cout[4]);


--E1L34 is minute:u4|i134~91
--operation mode is normal

E1L34 = M12_cs_buffer[5] & (M03_cs_buffer[5] # E1L64) # !M12_cs_buffer[5] & M03_cs_buffer[5] & !E1L64;


--E1L24 is minute:u4|i133~91
--operation mode is normal

E1L24 = K7_unreg_res_node[6] & (K01_unreg_res_node[6] # E1L64) # !K7_unreg_res_node[6] & K01_unreg_res_node[6] & !E1L64;


--F1L52 is act:u5|i82~562
--operation mode is normal

F1L52 = F1L76 # set_clk & !E1_clkhour[6] # !set_clk & !E1_count[6];


--F1L72 is act:u5|i82~565
--operation mode is normal

F1L72 = (set_clk & !D1_clkmin[6] # !set_clk & !D1_count[6] # !F1L42) & CASCADE(F1L52);


--F1L03 is act:u5|i83~536
--operation mode is normal

F1L03 = F1L76 # set_clk & !E1_clkhour[5] # !set_clk & !E1_count[5];


--F1L23 is act:u5|i83~539
--operation mode is normal

F1L23 = (set_clk & !D1_clkmin[5] # !set_clk & !D1_count[5] # !F1L42) & CASCADE(F1L03);


--K1_unreg_res_node[6] is msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|unreg_res_node[6]
--operation mode is normal

K1_unreg_res_node[6] = M3_cout[5] $ C1_count[6];


--K2_unreg_res_node[6] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|unreg_res_node[6]
--operation mode is normal

K2_unreg_res_node[6] = M6_cout[5] $ C1_count[6];


--K4_unreg_res_node[6] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|unreg_res_node[6]
--operation mode is normal

K4_unreg_res_node[6] = M21_cout[5] $ D1_clkmin[6];


--K6_unreg_res_node[6] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|unreg_res_node[6]
--operation mode is normal

K6_unreg_res_node[6] = M81_cout[5] $ D1_clkmin[6];


--K7_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[6]
--operation mode is normal

K7_unreg_res_node[6] = M12_cout[5] $ E1_clkhour[6];


--K01_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|unreg_res_node[6]
--operation mode is normal

K01_unreg_res_node[6] = M03_cout[5] $ E1_clkhour[6];


--F1L06 is act:u5|i224~121
--operation mode is normal

F1L06 = F1_num[2] & !F1_num[3] & (F1_num[1] # F1_num[0]) # !F1_num[2] & (F1_num[1] $ F1_num[3]);


--F1L5 is act:u5|daout1[0]~6
--operation mode is normal

F1L5 = F1L06 # F1L26;


--F1L75 is act:u5|i223~98
--operation mode is normal

F1L75 = F1_num[3] & !F1_num[1] & !F1_num[2] # !F1_num[3] & (F1_num[1] $ !F1_num[0] # !F1_num[2]);


--F1L85 is act:u5|i223~99
--operation mode is normal

F1L85 = F1_num[3] # F1_num[1] $ !F1_num[0] # !F1_num[2];


--F1L6 is act:u5|daout1[1]~5
--operation mode is normal

F1L6 = F1L75 & (F1L85 # !F1L6) # !F1L75 & F1L85 & F1L6;


--F1L25 is act:u5|i221~228
--operation mode is normal

F1L25 = F1L8 & (F1_num[3] # F1_num[2]) # !F1L8 & !F1_num[3] & F1_num[2] & !F1_num[1];


--F1L35 is act:u5|i221~229
--operation mode is normal

F1L35 = F1L8 & (F1_num[3] # F1_num[2] # !F1_num[1]) # !F1L8 & !F1_num[3] & (F1_num[2] $ !F1_num[1]);


--F1L15 is act:u5|i221~227
--operation mode is normal

F1L15 = F1L25 & (F1L35 # !F1_num[0]) # !F1L25 & F1L35 & F1_num[0];


--F1L21 is act:u5|dot~5
--operation mode is normal

F1L21 = !clr;


--B1L2 is any_even:u1|clk_outQ~1
--operation mode is normal

B1L2 = !B1L3;


--C1L6 is msecond:u2|count[3]~146
--operation mode is normal

C1L6 = !set;


--set_clk is set_clk
--operation mode is input

set_clk = INPUT();


--clk1 is clk1
--operation mode is input

clk1 = INPUT();


--set_hour is set_hour
--operation mode is input

set_hour = INPUT();


--en is en
--operation mode is input

en = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--set_fun is set_fun
--operation mode is input

set_fun = INPUT();


--set_min is set_min
--operation mode is input

set_min = INPUT();


--set is set
--operation mode is input

set = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--ss is ss
--operation mode is output

ss = OUTPUT(F1L31Q);


--alarm is alarm
--operation mode is output

alarm = OUTPUT(!A1L9);


--selout[5] is selout[5]
--operation mode is output

selout[5] = OUTPUT(F1_sel[5]);


--selout[4] is selout[4]
--operation mode is output

selout[4] = OUTPUT(F1_sel[4]);


--selout[3] is selout[3]
--operation mode is output

selout[3] = OUTPUT(F1_sel[3]);


--selout[2] is selout[2]
--operation mode is output

selout[2] = OUTPUT(F1_sel[2]);


--selout[1] is selout[1]
--operation mode is output

selout[1] = OUTPUT(F1_sel[1]);


--selout[0] is selout[0]
--operation mode is output

selout[0] = OUTPUT(F1_sel[0]);


--led[6] is led[6]
--operation mode is output

led[6] = OUTPUT(F1L11);


--led[5] is led[5]
--operation mode is output

led[5] = OUTPUT(!F1L01);


--led[4] is led[4]
--operation mode is output

led[4] = OUTPUT(F1L9);


--led[3] is led[3]
--operation mode is output

led[3] = OUTPUT(!F1L8);


--led[2] is led[2]
--operation mode is output

led[2] = OUTPUT(F1L7);


--led[1] is led[1]
--operation mode is output

led[1] = OUTPUT(F1L6);


--led[0] is led[0]
--operation mode is output

led[0] = OUTPUT(F1L5);