watch.map.eqn

可以实现时间调节

--operation mode is arithmetic

M81_cs_buffer[1] = D1_clkmin[1] $ M81_cout[0];

--M81_cout[1] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M81_cout[1] = CARRY(D1_clkmin[1] & M81_cout[0]);


--M51_cs_buffer[1] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M51_cs_buffer[1] = D1_count[1] $ M51_cout[0];

--M51_cout[1] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M51_cout[1] = CARRY(D1_count[1] & M51_cout[0]);


--E1L13 is minute:u4|i27~0
--operation mode is normal

E1L13 = E1_clkhour[3] & (E1L13 # set_clk) # !E1_clkhour[3] & E1L13 & !set_clk;


--D1L82 is second:u3|i13~0
--operation mode is normal

D1L82 = D1_clkmin[4] & (D1L82 # set_clk) # !D1_clkmin[4] & D1L82 & !set_clk;


--E1L73 is minute:u4|i30~0
--operation mode is normal

E1L73 = E1_clkhour[0] & (E1L73 # set_clk) # !E1_clkhour[0] & E1L73 & !set_clk;


--D1L03 is second:u3|i14~0
--operation mode is normal

D1L03 = D1_clkmin[3] & (D1L03 # set_clk) # !D1_clkmin[3] & D1L03 & !set_clk;


--M81_cs_buffer[3] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M81_cs_buffer[3] = D1_clkmin[3] $ M81_cout[2];

--M81_cout[3] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M81_cout[3] = CARRY(D1_clkmin[3] & M81_cout[2]);


--M51_cs_buffer[3] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M51_cs_buffer[3] = D1_count[3] $ M51_cout[2];

--M51_cout[3] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M51_cout[3] = CARRY(D1_count[3] & M51_cout[2]);


--D1L23 is second:u3|i15~0
--operation mode is normal

D1L23 = D1_clkmin[2] & (D1L23 # set_clk) # !D1_clkmin[2] & D1L23 & !set_clk;


--D1L63 is second:u3|i17~0
--operation mode is normal

D1L63 = D1_clkmin[0] & (D1L63 # set_clk) # !D1_clkmin[0] & D1L63 & !set_clk;


--D1_clkmin[0] is second:u3|clkmin[0]
--operation mode is normal

D1_clkmin[0]_lut_out = D1L94 & !M81_cs_buffer[0];
D1_clkmin[0] = DFFEA(D1_clkmin[0]_lut_out, set_min, , , E1L3, , );


--D1_count[0] is second:u3|count[0]
--operation mode is normal

D1_count[0]_lut_out = D1L44 & !M51_cs_buffer[0];
D1_count[0] = DFFEA(D1_count[0]_lut_out, D1L83, !clr, , E1L21, , );


--M81_cs_buffer[2] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M81_cs_buffer[2] = D1_clkmin[2] $ M81_cout[1];

--M81_cout[2] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M81_cout[2] = CARRY(D1_clkmin[2] & M81_cout[1]);


--M51_cs_buffer[2] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M51_cs_buffer[2] = D1_count[2] $ M51_cout[1];

--M51_cout[2] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M51_cout[2] = CARRY(D1_count[2] & M51_cout[1]);


--F1L81 is act:u5|i82~549
--operation mode is normal

F1L81 = F1_count[2] & !F1_count[1] & !F1_count[0];


--C1_count[3] is msecond:u2|count[3]
--operation mode is normal

C1_count[3]_lut_out = M6_cs_buffer[3] & C1L61;
C1_count[3] = DFFEA(C1_count[3]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--F1L41 is act:u5|i81~348
--operation mode is normal

F1L41 = F1L36 & F1_num[3] # !F1L36 & C1_count[3] & !set_clk;


--F1L91 is act:u5|i82~552
--operation mode is normal

F1L91 = F1_count[2] # F1_count[0] $ !F1_count[1];


--F1L51 is act:u5|i81~349
--operation mode is normal

F1L51 = F1L41 & F1L56 & F1L66 & F1L91;


--F1L61 is act:u5|i81~350
--operation mode is normal

F1L61 = F1_count[1] & !F1_count[2] & !F1_count[0];


--F1L71 is act:u5|i81~351
--operation mode is normal

F1L71 = F1L66 & D1L02 & F1L61 # !F1L66 & E1L12;


--F1L84 is act:u5|i219~150
--operation mode is normal

F1L84 = F1L74 & F1_num[0] & !F1_num[3] # !F1L74 & (F1L01 # !F1_num[3]);


--F1L01 is act:u5|daout1[5]~31
--operation mode is normal

F1L01 = (F1_num[3] # F1_num[1] & F1_num[0] # !F1_num[2]) & CASCADE(F1L84);


--F1L8 is act:u5|daout1[3]~32
--operation mode is normal

F1L8 = (F1_num[3] & (F1_num[1] # F1_num[2]) # !F1_num[3] & (F1_num[1] $ !F1_num[0] # !F1_num[2])) & CASCADE(F1L15);


--F1L16 is act:u5|i224~125
--operation mode is normal

F1L16 = F1L5 # F1L74 & !F1_num[3] & !F1_num[0];


--F1L26 is act:u5|i224~127
--operation mode is normal

F1L26 = (F1_num[3] # F1_num[1] # F1_num[0] $ !F1_num[2]) & CASCADE(F1L16);


--M72_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M72_cs_buffer[4] = E1_count[4] $ M72_cout[3];

--M72_cout[4] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M72_cout[4] = CARRY(E1_count[4] & M72_cout[3]);


--M42_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M42_cs_buffer[4] = E1_count[4] $ M42_cout[3];

--M42_cout[4] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M42_cout[4] = CARRY(E1_count[4] & M42_cout[3]);


--E1L14 is minute:u4|i85~165
--operation mode is normal

E1L14 = M72_cs_buffer[4] & (M42_cs_buffer[4] # E1L45) # !M72_cs_buffer[4] & M42_cs_buffer[4] & !E1L45;


--E1L93 is minute:u4|i83~161
--operation mode is normal

E1L93 = K9_unreg_res_node[6] & (K8_unreg_res_node[6] # E1L45) # !K9_unreg_res_node[6] & K8_unreg_res_node[6] & !E1L45;


--M72_cs_buffer[5] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M72_cs_buffer[5] = E1_count[5] $ M72_cout[4];

--M72_cout[5] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M72_cout[5] = CARRY(E1_count[5] & M72_cout[4]);


--M42_cs_buffer[5] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M42_cs_buffer[5] = E1_count[5] $ M42_cout[4];

--M42_cout[5] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M42_cout[5] = CARRY(E1_count[5] & M42_cout[4]);


--E1L04 is minute:u4|i84~161
--operation mode is normal

E1L04 = M72_cs_buffer[5] & (M42_cs_buffer[5] # E1L45) # !M72_cs_buffer[5] & M42_cs_buffer[5] & !E1L45;


--C1_count[4] is msecond:u2|count[4]
--operation mode is normal

C1_count[4]_lut_out = C1L51;
C1_count[4] = DFFEA(C1_count[4]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[6] is msecond:u2|count[6]
--operation mode is normal

C1_count[6]_lut_out = C1L31;
C1_count[6] = DFFEA(C1_count[6]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[2] is msecond:u2|count[2]
--operation mode is normal

C1_count[2]_lut_out = M6_cs_buffer[2] & C1L61;
C1_count[2] = DFFEA(C1_count[2]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[1] is msecond:u2|count[1]
--operation mode is normal

C1_count[1]_lut_out = M6_cs_buffer[1] & C1L61;
C1_count[1] = DFFEA(C1_count[1]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1L81 is msecond:u2|i~80
--operation mode is normal

C1L81 = C1_count[0] & C1_count[3] & !C1_count[2] & !C1_count[1];


--C1_count[5] is msecond:u2|count[5]
--operation mode is normal

C1_count[5]_lut_out = C1L41;
C1_count[5] = DFFEA(C1_count[5]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1L71 is msecond:u2|i55~91
--operation mode is normal

C1L71 = C1_count[4] & C1_count[6] & C1L81 & !C1_count[5];


--C1L61 is msecond:u2|i51~68
--operation mode is normal

C1L61 = !C1L81 & (!C1_count[5] # !C1_count[6]);


--B1L4 is any_even:u1|i~319
--operation mode is normal

B1L4 = H1_q[23] # H1_q[21] # H1_q[20] # !H1_q[22];


--B1L5 is any_even:u1|i~320
--operation mode is normal

B1L5 = H1_q[17] # H1_q[16] # !H1_q[18] # !H1_q[19];


--B1L3 is any_even:u1|i~1
--operation mode is normal

B1L3 = B1L4 # B1L5 # !B1L9 # !B1L8;


--D1_clkmin[5] is second:u3|clkmin[5]
--operation mode is normal

D1_clkmin[5]_lut_out = D1L64;
D1_clkmin[5] = DFFEA(D1_clkmin[5]_lut_out, set_min, , , E1L3, , );


--D1_clkmin[6] is second:u3|clkmin[6]
--operation mode is normal

D1_clkmin[6]_lut_out = D1L54;
D1_clkmin[6] = DFFEA(D1_clkmin[6]_lut_out, set_min, , , E1L3, , );


--D1L15 is second:u3|i~154
--operation mode is normal

D1L15 = D1_clkmin[3] & D1_clkmin[0] & !D1_clkmin[1] & !D1_clkmin[2];


--D1L94 is second:u3|i128~42
--operation mode is normal

D1L94 = !D1L15 & (!D1_clkmin[6] # !D1_clkmin[5]);


--E1_clkhour[5] is minute:u4|clkhour[5]
--operation mode is normal

E1_clkhour[5]_lut_out = E1L34 & E1L84;
E1_clkhour[5] = DFFEA(E1_clkhour[5]_lut_out, set_hour, , , E1L3, , );


--E1_clkhour[6] is minute:u4|clkhour[6]
--operation mode is normal

E1_clkhour[6]_lut_out = E1L24 & E1L84;
E1_clkhour[6] = DFFEA(E1_clkhour[6]_lut_out, set_hour, , , E1L3, , );


--E1L74 is minute:u4|i139~273
--operation mode is normal

E1L74 = !E1_clkhour[5] & !E1_clkhour[6] & (!set_fun # !E1_clkhour[4]);


--E1L84 is minute:u4|i139~274
--operation mode is normal

E1L84 = E1L74 & (E1L35 # E1L64) # !E1L74 & E1L35 & !E1L64;


--M12_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M12_cs_buffer[4] = E1_clkhour[4] $ M12_cout[3];

--M12_cout[4] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M12_cout[4] = CARRY(E1_clkhour[4] & M12_cout[3]);


--M03_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M03_cs_buffer[4] = E1_clkhour[4] $ M03_cout[3];

--M03_cout[4] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M03_cout[4] = CARRY(E1_clkhour[4] & M03_cout[3]);


--E1L44 is minute:u4|i135~91
--operation mode is normal

E1L44 = M12_cs_buffer[4] & (M03_cs_buffer[4] # E1L64) # !M12_cs_buffer[4] & M03_cs_buffer[4] & !E1L64;


--M81_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M81_cs_buffer[4] = D1_clkmin[4] $ M81_cout[3];

--M81_cout[4] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M81_cout[4] = CARRY(D1_clkmin[4] & M81_cout[3]);


--M21_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M21_cs_buffer[4] = D1_clkmin[4] $ M21_cout[3];

--M21_cout[4] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M21_cout[4] = CARRY(D1_clkmin[4] & M21_cout[3]);


--D1L74 is second:u3|i124~109
--operation mode is normal

D1L74 = D1L15 & (!D1_clkmin[4] & !D1_clkmin[5] # !D1_clkmin[6]);


--D1L84 is second:u3|i124~110
--operation mode is normal

D1L84 = M81_cs_buffer[4] & (D1L94 # M21_cs_buffer[4] & D1L74) # !M81_cs_buffer[4] & M21_cs_buffer[4] & D1L74;


--M51_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M51_cs_buffer[4] = D1_count[4] $ M51_cout[3];

--M51_cout[4] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M51_cout[4] = CARRY(D1_count[4] & M51_cout[3]);


--M9_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M9_cs_buffer[4] = D1_count[4] $ M9_cout[3];

--M9_cout[4] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M9_cout[4] = CARRY(D1_count[4] & M9_cout[3]);


--D1L24 is second:u3|i76~97
--operation mode is normal

D1L24 = D1L05 & (!D1_count[5] & !D1_count[4] # !D1_count[6]);


--D1L34 is second:u3|i76~98
--operation mode is normal

D1L34 = M51_cs_buffer[4] & (D1L44 # M9_cs_buffer[4] & D1L24) # !M51_cs_buffer[4] & M9_cs_buffer[4] & D1L24;


--i16 is i16
--operation mode is normal

i16 = E1L72 $ (set_clk & !E1_clkhour[5] # !set_clk & !E1_count[5]);


--A1L41 is i27~222
--operation mode is normal

A1L41 = (D1L62 $ (set_clk & !D1_clkmin[5] # !set_clk & !D1_count[5])) & CASCADE(i16);


--i25 is i25
--operation mode is normal

i25 = D1L42 $ (set_clk & !D1_clkmin[6] # !set_clk & !D1_count[6]);


--A1L51 is i27~223
--operation mode is normal

A1L51 = (E1L52 $ (set_clk & !E1_clkhour[6] # !set_clk & !E1_count[6])) & CASCADE(i25);


--M81_cs_buffer[0] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

M81_cs_buffer[0] = D1_clkmin[0];

--M81_cout[0] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

M81_cout[0] = CARRY(D1_clkmin[0]);


--M51_cs_buffer[0] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

M51_cs_buffer[0] = D1_count[0];

--M51_cout[0] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

M51_cout[0] = CARRY(D1_count[0]);


--F1L02 is act:u5|i82~554
--operation mode is normal

F1L02 = F1L36 & F1_num[2] # !F1L36 & C1_count[2] & !set_clk;


--F1L12 is act:u5|i82~555
--operation mode is normal

F1L12 = F1L46 & F1L24 & F1_count[0] & !set_clk;


--F1L22 is act:u5|i82~556
--operation mode is normal

F1L22 = C1_count[6] & (F1L12 # D1L12 & !F1L46) # !C1_count[6] & D1L12 & !F1L46;


--F1L32 is act:u5|i82~557
--operation mode is normal

F1L32 = F1L56 & F1L66 & F1L76;


--F1L62 is act:u5|i82~564
--operation mode is normal

F1L62 = (!F1L22 & (!F1L02 # !F1L91) # !F1L32) & CASCADE(F1L72);


--F1L82 is act:u5|i83~531
--operation mode is normal

F1L82 = F1L36 & F1_num[1] # !F1L36 & C1_count[1] & !set_clk;


--F1L92 is act:u5|i83~532
--operation mode is normal

F1L92 = C1_count[5] & (F1L12 # D1L22 & !F1L46) # !C1_count[5] & D1L22 & !F1L46;


--F1L13 is act:u5|i83~538
--operation mode is normal

F1L13 = (!F1L92 & (!F1L82 # !F1L91) # !F1L32) & CASCADE(F1L23);


--F1L42 is act:u5|i82~559
--operation mode is normal

F1L42 = F1L66 & F1L76 & !F1L56;


--F1L33 is act:u5|i84~526
--operation mode is normal

F1L33 = F1L76 & (!F1L42 # !D1L91) # !F1L76 & !E1L02 & (!F1L42 # !D1L91);


--F1L43 is act:u5|i84~527
--operation mode is normal

F1L43 = F1L36 & F1_num[0] # !F1L36 & C1_count[0] & !set_clk;