watch.fit.eqn

可以实现时间调节

--M42_cs_buffer[5] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC6_A4
--operation mode is arithmetic

M42_cs_buffer[5] = E1_count[5] $ M42_cout[4];

--M42_cout[5] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5] at LC6_A4
--operation mode is arithmetic

M42_cout[5] = CARRY(E1_count[5] & M42_cout[4]);


--E1L04 is minute:u4|i84~161 at LC1_A4
--operation mode is normal

E1L04 = E1L45 & M72_cs_buffer[5] # !E1L45 & M42_cs_buffer[5];


--C1_count[4] is msecond:u2|count[4] at LC5_C7
--operation mode is normal

C1_count[4]_lut_out = C1L51;
C1_count[4] = DFFEA(C1_count[4]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[6] is msecond:u2|count[6] at LC8_C8
--operation mode is normal

C1_count[6]_lut_out = C1L31;
C1_count[6] = DFFEA(C1_count[6]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[2] is msecond:u2|count[2] at LC1_C8
--operation mode is normal

C1_count[2]_lut_out = C1L61 & M6_cs_buffer[2];
C1_count[2] = DFFEA(C1_count[2]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1_count[1] is msecond:u2|count[1] at LC4_C8
--operation mode is normal

C1_count[1]_lut_out = C1L61 & M6_cs_buffer[1];
C1_count[1] = DFFEA(C1_count[1]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1L81 is msecond:u2|i~80 at LC3_C7
--operation mode is normal

C1L81 = !C1_count[1] & !C1_count[2] & C1_count[3] & C1_count[0];


--C1_count[5] is msecond:u2|count[5] at LC6_C8
--operation mode is normal

C1_count[5]_lut_out = C1L41;
C1_count[5] = DFFEA(C1_count[5]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--C1L71 is msecond:u2|i55~91 at LC6_C7
--operation mode is normal

C1L71 = !C1_count[5] & C1L81 & C1_count[6] & C1_count[4];


--C1L61 is msecond:u2|i51~68 at LC8_C7
--operation mode is normal

C1L61 = !C1L81 & (!C1_count[6] # !C1_count[5]);


--B1L4 is any_even:u1|i~319 at LC2_B9
--operation mode is normal

B1L4 = H1_q[20] # H1_q[21] # H1_q[23] # !H1_q[22];


--B1L5 is any_even:u1|i~320 at LC3_B9
--operation mode is normal

B1L5 = H1_q[16] # H1_q[17] # !H1_q[19] # !H1_q[18];


--B1L3 is any_even:u1|i~1 at LC1_B9
--operation mode is normal

B1L3 = B1L5 # B1L4 # !B1L8 # !B1L9;


--D1_clkmin[5] is second:u3|clkmin[5] at LC5_B13
--operation mode is normal

D1_clkmin[5]_lut_out = D1L64;
D1_clkmin[5] = DFFEA(D1_clkmin[5]_lut_out, GLOBAL(set_min), , , E1L3, , );


--D1_clkmin[6] is second:u3|clkmin[6] at LC4_B13
--operation mode is normal

D1_clkmin[6]_lut_out = D1L54;
D1_clkmin[6] = DFFEA(D1_clkmin[6]_lut_out, GLOBAL(set_min), , , E1L3, , );


--D1L15 is second:u3|i~154 at LC1_B14
--operation mode is normal

D1L15 = !D1_clkmin[2] & !D1_clkmin[1] & D1_clkmin[0] & D1_clkmin[3];


--D1L94 is second:u3|i128~42 at LC1_B13
--operation mode is normal

D1L94 = !D1L15 & (!D1_clkmin[5] # !D1_clkmin[6]);


--E1_clkhour[5] is minute:u4|clkhour[5] at LC8_A1
--operation mode is normal

E1_clkhour[5]_lut_out = E1L84 & E1L34;
E1_clkhour[5] = DFFEA(E1_clkhour[5]_lut_out, GLOBAL(set_hour), , , E1L3, , );


--E1_clkhour[6] is minute:u4|clkhour[6] at LC6_A1
--operation mode is normal

E1_clkhour[6]_lut_out = E1L84 & E1L24;
E1_clkhour[6] = DFFEA(E1_clkhour[6]_lut_out, GLOBAL(set_hour), , , E1L3, , );


--E1L74 is minute:u4|i139~273 at LC2_A1
--operation mode is normal

E1L74 = !E1_clkhour[6] & !E1_clkhour[5] & (!E1_clkhour[4] # !set_fun);


--E1L84 is minute:u4|i139~274 at LC3_A1
--operation mode is normal

E1L84 = E1L64 & E1L74 # !E1L64 & E1L35;


--M12_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_A7
--operation mode is arithmetic

M12_cs_buffer[4] = E1_clkhour[4] $ M12_cout[3];

--M12_cout[4] is minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_A7
--operation mode is arithmetic

M12_cout[4] = CARRY(E1_clkhour[4] & M12_cout[3]);


--M03_cs_buffer[4] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_A8
--operation mode is arithmetic

M03_cs_buffer[4] = E1_clkhour[4] $ M03_cout[3];

--M03_cout[4] is minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_A8
--operation mode is arithmetic

M03_cout[4] = CARRY(E1_clkhour[4] & M03_cout[3]);


--E1L44 is minute:u4|i135~91 at LC4_A1
--operation mode is normal

E1L44 = E1L64 & M12_cs_buffer[4] # !E1L64 & M03_cs_buffer[4];


--M81_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_B15
--operation mode is arithmetic

M81_cs_buffer[4] = D1_clkmin[4] $ M81_cout[3];

--M81_cout[4] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_B15
--operation mode is arithmetic

M81_cout[4] = CARRY(D1_clkmin[4] & M81_cout[3]);


--M21_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC6_B14
--operation mode is arithmetic

M21_cs_buffer[4] = D1_clkmin[4] $ M21_cout[3];

--M21_cout[4] is second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] at LC6_B14
--operation mode is arithmetic

M21_cout[4] = CARRY(D1_clkmin[4] & M21_cout[3]);


--D1L74 is second:u3|i124~109 at LC3_B13
--operation mode is normal

D1L74 = D1L15 & (!D1_clkmin[5] & !D1_clkmin[4] # !D1_clkmin[6]);


--D1L84 is second:u3|i124~110 at LC6_B13
--operation mode is normal

D1L84 = D1L94 & (M81_cs_buffer[4] # D1L74 & M21_cs_buffer[4]) # !D1L94 & D1L74 & M21_cs_buffer[4];


--M51_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_A19
--operation mode is arithmetic

M51_cs_buffer[4] = D1_count[4] $ M51_cout[3];

--M51_cout[4] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_A19
--operation mode is arithmetic

M51_cout[4] = CARRY(D1_count[4] & M51_cout[3]);


--M9_cs_buffer[4] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC5_A13
--operation mode is arithmetic

M9_cs_buffer[4] = D1_count[4] $ M9_cout[3];

--M9_cout[4] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] at LC5_A13
--operation mode is arithmetic

M9_cout[4] = CARRY(D1_count[4] & M9_cout[3]);


--D1L24 is second:u3|i76~97 at LC1_A17
--operation mode is normal

D1L24 = D1L05 & (!D1_count[4] & !D1_count[5] # !D1_count[6]);


--D1L34 is second:u3|i76~98 at LC8_A13
--operation mode is normal

D1L34 = D1L44 & (M51_cs_buffer[4] # D1L24 & M9_cs_buffer[4]) # !D1L44 & D1L24 & M9_cs_buffer[4];


--i16 is i16 at LC5_A6
--operation mode is normal

i16 = E1L72 $ (set_clk & !E1_clkhour[5] # !set_clk & !E1_count[5]);


--A1L41 is i27~222 at LC6_A6
--operation mode is normal

A1L41 = (D1L62 $ (set_clk & !D1_clkmin[5] # !set_clk & !D1_count[5])) & CASCADE(i16);


--i25 is i25 at LC3_A16
--operation mode is normal

i25 = D1L42 $ (set_clk & !D1_clkmin[6] # !set_clk & !D1_count[6]);


--A1L51 is i27~223 at LC4_A16
--operation mode is normal

A1L51 = (E1L52 $ (set_clk & !E1_clkhour[6] # !set_clk & !E1_count[6])) & CASCADE(i25);


--M81_cs_buffer[0] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] at LC1_B15
--operation mode is arithmetic

M81_cs_buffer[0] = D1_clkmin[0];

--M81_cout[0] is second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node|cout[0] at LC1_B15
--operation mode is arithmetic

M81_cout[0] = CARRY(D1_clkmin[0]);


--M51_cs_buffer[0] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] at LC1_A19
--operation mode is arithmetic

M51_cs_buffer[0] = D1_count[0];

--M51_cout[0] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[0] at LC1_A19
--operation mode is arithmetic

M51_cout[0] = CARRY(D1_count[0]);


--F1L02 is act:u5|i82~554 at LC5_C13
--operation mode is normal

F1L02 = F1L36 & F1_num[2] # !F1L36 & !set_clk & C1_count[2];


--F1L12 is act:u5|i82~555 at LC6_C13
--operation mode is normal

F1L12 = !set_clk & F1_count[0] & F1L24 & F1L46;


--F1L22 is act:u5|i82~556 at LC7_C13
--operation mode is normal

F1L22 = F1L46 & F1L12 & C1_count[6] # !F1L46 & (D1L12 # F1L12 & C1_count[6]);


--F1L32 is act:u5|i82~557 at LC5_C18
--operation mode is normal

F1L32 = F1L76 & F1L66 & F1L56;


--F1L62 is act:u5|i82~564 at LC3_C13
--operation mode is normal

F1L62 = (!F1L22 & (!F1L91 # !F1L02) # !F1L32) & CASCADE(F1L72);


--F1L82 is act:u5|i83~531 at LC5_C16
--operation mode is normal

F1L82 = F1L36 & F1_num[1] # !F1L36 & !set_clk & C1_count[1];


--F1L92 is act:u5|i83~532 at LC6_C16
--operation mode is normal

F1L92 = F1L46 & F1L12 & C1_count[5] # !F1L46 & (D1L22 # F1L12 & C1_count[5]);


--F1L13 is act:u5|i83~538 at LC4_C16
--operation mode is normal

F1L13 = (!F1L92 & (!F1L91 # !F1L82) # !F1L32) & CASCADE(F1L23);


--F1L42 is act:u5|i82~559 at LC2_C18
--operation mode is normal

F1L42 = !F1L56 & F1L76 & F1L66;


--F1L33 is act:u5|i84~526 at LC7_C15
--operation mode is normal

F1L33 = F1L42 & !D1L91 & (F1L76 # !E1L02) # !F1L42 & (F1L76 # !E1L02);


--F1L43 is act:u5|i84~527 at LC2_C15
--operation mode is normal

F1L43 = F1L36 & F1_num[0] # !F1L36 & !set_clk & C1_count[0];


--F1L53 is act:u5|i84~528 at LC3_C15
--operation mode is normal

F1L53 = F1L46 & F1L12 & C1_count[4] # !F1L46 & (D1L32 # F1L12 & C1_count[4]);


--F1L63 is act:u5|i84~530 at LC8_C15
--operation mode is normal

F1L63 = (!F1L53 & (!F1L91 # !F1L43) # !F1L32) & CASCADE(F1L33);


--M6_cs_buffer[3] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC4_C6
--operation mode is arithmetic

M6_cs_buffer[3] = C1_count[3] $ M6_cout[2];

--M6_cout[3] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[3] at LC4_C6
--operation mode is arithmetic

M6_cout[3] = CARRY(C1_count[3] & M6_cout[2]);


--K9_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|unreg_res_node[6] at LC7_A5
--operation mode is normal

K9_unreg_res_node[6] = M72_cout[5] $ E1_count[6];


--K8_unreg_res_node[6] is minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|unreg_res_node[6] at LC7_A4
--operation mode is normal

K8_unreg_res_node[6] = M42_cout[5] $ E1_count[6];


--D1L04 is second:u3|i74~96 at LC8_A17
--operation mode is normal

D1L04 = K5_unreg_res_node[6] & (D1L44 # K3_unreg_res_node[6] & D1L24) # !K5_unreg_res_node[6] & K3_unreg_res_node[6] & D1L24;


--M9_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC6_A13
--operation mode is arithmetic

M9_cs_buffer[5] = D1_count[5] $ M9_cout[4];

--M9_cout[5] is second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] at LC6_A13
--operation mode is arithmetic

M9_cout[5] = CARRY(D1_count[5] & M9_cout[4]);


--M51_cs_buffer[5] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC6_A19
--operation mode is arithmetic

M51_cs_buffer[5] = D1_count[5] $ M51_cout[4];

--M51_cout[5] is second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node|cout[5] at LC6_A19
--operation mode is arithmetic

M51_cout[5] = CARRY(D1_count[5] & M51_cout[4]);


--D1L14 is second:u3|i75~96 at LC1_A14
--operation mode is normal

D1L14 = M51_cs_buffer[5] & (D1L44 # M9_cs_buffer[5] & D1L24) # !M51_cs_buffer[5] & M9_cs_buffer[5] & D1L24;


--C1_count[0] is msecond:u2|count[0] at LC2_C8
--operation mode is normal

C1_count[0]_lut_out = !M6_cs_buffer[0] & C1L61;
C1_count[0] = DFFEA(C1_count[0]_lut_out, B1_clk_outQ, !clr, , C1L6, , );


--M6_cs_buffer[2] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC3_C6
--operation mode is arithmetic

M6_cs_buffer[2] = C1_count[2] $ M6_cout[1];

--M6_cout[2] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[2] at LC3_C6
--operation mode is arithmetic

M6_cout[2] = CARRY(C1_count[2] & M6_cout[1]);


--M6_cs_buffer[1] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC2_C6
--operation mode is arithmetic

M6_cs_buffer[1] = C1_count[1] $ M6_cout[0];

--M6_cout[1] is msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node|cout[1] at LC2_C6
--operation mode is arithmetic

M6_cout[1] = CARRY(C1_count[1] & M6_cout[0]);


--E1L72 is minute:u4|i25~0 at LC2_A12
--operation mode is normal

E1L72 = set_clk & E1_clkhour[5] # !set_clk & E1L72;


--D1L62 is second:u3|i12~0 at LC8_A6
--operation mode is normal

D1L62 = set_clk & D1_clkmin[5] # !set_clk & D1L62;


--D1L42 is second:u3|i11~0 at LC7_A16
--operation mode is normal