📄 watch.map.rpt
字号:
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:i_rtl_7
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- act:u5
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------+
; |watch ; 284 (10) ; 76 ; 0 ; 24 ; 208 (10) ; 12 (0) ; 64 (0) ; 89 (0) ; |watch ;
; |act:u5| ; 72 (72) ; 14 ; 0 ; 0 ; 58 (58) ; 2 (2) ; 12 (12) ; 0 (0) ; |watch|act:u5 ;
; |any_even:u1| ; 33 (9) ; 25 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 24 (0) ; 24 (0) ; |watch|any_even:u1 ;
; |lpm_counter:coutQ_rtl_0| ; 24 (0) ; 24 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (0) ; 24 (0) ; |watch|any_even:u1|lpm_counter:coutQ_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 24 (24) ; 24 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; 24 (24) ; |watch|any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter ;
; |minute:u4| ; 71 (45) ; 14 ; 0 ; 0 ; 57 (31) ; 0 (0) ; 14 (14) ; 26 (0) ; |watch|minute:u4 ;
; |lpm_add_sub:i_rtl_1| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; |watch|minute:u4|lpm_add_sub:i_rtl_1 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; |watch|minute:u4|lpm_add_sub:i_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; |watch|minute:u4|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_2| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; |watch|minute:u4|lpm_add_sub:i_rtl_2 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; |watch|minute:u4|lpm_add_sub:i_rtl_2|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; |watch|minute:u4|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_6| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |watch|minute:u4|lpm_add_sub:i_rtl_6 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |watch|minute:u4|lpm_add_sub:i_rtl_6|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |watch|minute:u4|lpm_add_sub:i_rtl_6|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_7| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |watch|minute:u4|lpm_add_sub:i_rtl_7 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |watch|minute:u4|lpm_add_sub:i_rtl_7|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |watch|minute:u4|lpm_add_sub:i_rtl_7|addcore:adder|a_csnbuffer:result_node ;
; |msecond:u2| ; 30 (17) ; 8 ; 0 ; 0 ; 22 (9) ; 3 (3) ; 5 (5) ; 13 (0) ; |watch|msecond:u2 ;
; |lpm_add_sub:i_rtl_10| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |watch|msecond:u2|lpm_add_sub:i_rtl_10 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |watch|msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |watch|msecond:u2|lpm_add_sub:i_rtl_10|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_5| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; |watch|msecond:u2|lpm_add_sub:i_rtl_5 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; |watch|msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; |watch|msecond:u2|lpm_add_sub:i_rtl_5|addcore:adder|a_csnbuffer:result_node ;
; |second:u3| ; 68 (42) ; 15 ; 0 ; 0 ; 53 (27) ; 6 (6) ; 9 (9) ; 26 (0) ; |watch|second:u3 ;
; |lpm_add_sub:i_rtl_3| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; |watch|second:u3|lpm_add_sub:i_rtl_3 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; |watch|second:u3|lpm_add_sub:i_rtl_3|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; |watch|second:u3|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_4| ; 6 (0) ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; |watch|second:u3|lpm_add_sub:i_rtl_4 ;
; |addcore:adder| ; 6 (1) ; 0 ; 0 ; 0 ; 6 (1) ; 0 (0) ; 0 (0) ; 6 (1) ; |watch|second:u3|lpm_add_sub:i_rtl_4|addcore:adder ;
; |a_csnbuffer:result_node| ; 5 (5) ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; |watch|second:u3|lpm_add_sub:i_rtl_4|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_8| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |watch|second:u3|lpm_add_sub:i_rtl_8 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |watch|second:u3|lpm_add_sub:i_rtl_8|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |watch|second:u3|lpm_add_sub:i_rtl_8|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:i_rtl_9| ; 7 (0) ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; |watch|second:u3|lpm_add_sub:i_rtl_9 ;
; |addcore:adder| ; 7 (1) ; 0 ; 0 ; 0 ; 7 (1) ; 0 (0) ; 0 (0) ; 7 (1) ; |watch|second:u3|lpm_add_sub:i_rtl_9|addcore:adder ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; |watch|second:u3|lpm_add_sub:i_rtl_9|addcore:adder|a_csnbuffer:result_node ;
+-------------------------------------------+-------------+-----------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in E:/王明/shiyan10/watch.map.eqn.
+-----------------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+------------------------------------------------------------------
; File Name ; Read ;
+----------------------------------------------------------+------+
; act.vhd ; Read ;
; any_even.vhd ; Read ;
; minute.vhd ; Read ;
; msecond.vhd ; Read ;
; second.vhd ; Read ;
; watch.vhd ; Read ;
; c:/quartus/libraries/megafunctions/lpm_counter.tdf ; Read ;
; c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ; Read ;
; c:/quartus/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; c:/quartus/libraries/megafunctions/addcore.tdf ; Read ;
; c:/quartus/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; c:/quartus/libraries/megafunctions/altshift.tdf ; Read ;
+----------------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+-------------------------------+-------------+
; Logic cells ; 284 ;
; Total combinational functions ; 272 ;
; Total registers ; 76 ;
; I/O pins ; 24 ;
; Maximum fan-out node ; set_clk ;
; Maximum fan-out ; 41 ;
; Total fan-out ; 944 ;
; Average fan-out ; 3.06 ;
+-------------------------------+-------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 43 ;
; Number of synthesis-generated cells ; 241 ;
; Number of WYSIWYG LUTs ; 43 ;
; Number of synthesis-generated LUTs ; 229 ;
; Number of WYSIWYG registers ; 24 ;
; Number of synthesis-generated registers ; 52 ;
; Number of cells with combinational logic only ; 208 ;
; Number of cells with registers only ; 12 ;
; Number of cells with combinational logic and registers ; 64 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 24 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 24 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 49 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Wed Dec 03 14:39:56 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off watch -c watch
Info: Found 2 design units and 1 entities in source file act.vhd
Info: Found design unit 1: act-fun
Info: Found entity 1: act
Info: Found 2 design units and 1 entities in source file any_even.vhd
Info: Found design unit 1: any_even-div1
Info: Found entity 1: any_even
Info: Found 2 design units and 1 entities in source file minute.vhd
Info: Found design unit 1: minute-fun
Info: Found entity 1: minute
Info: Found 2 design units and 1 entities in source file msecond.vhd
Info: Found design unit 1: msecond-fun
Info: Found entity 1: msecond
Info: Found 2 design units and 1 entities in source file second.vhd
Info: Found design unit 1: second-fun
Info: Found entity 1: second
Info: Found 2 design units and 1 entities in source file watch.vhd
Info: Found design unit 1: watch-behave
Info: Found entity 1: watch
Warning: VHDL Process Statement warning at minute.vhd(53): signal set_clk is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at minute.vhd(72): signal set_hour is in statement, but is not in sensitivity list
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: any_even:u1|coutQ[0]~0
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Implemented 308 device resources after synthesis - the final resource count might be different
Info: Implemented 9 input pins
Info: Implemented 15 output pins
Info: Implemented 284 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Dec 03 14:40:04 2008
Info: Elapsed time: 00:00:08
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