watch.vhd

来自「可以实现时间调节」· VHDL 代码 · 共 92 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity watch is
port(clk,clk1: in std_logic;
   clr: in std_logic;
     set: in std_logic;
     en:  in std_logic;
set_clk:  in std_logic;
set_hour: in std_logic;
set_min:  in std_logic;
set_fun:  in std_logic;
     ss:out std_logic;
  alarm: out std_logic;
     selout: out std_logic_vector( 5 downto 0);
     led: out   std_logic_vector(6 downto 0));
end entity watch;

architecture behave of watch is


component msecond is
port(
		clk, clr,set    : in	std_logic;
		ensec             : out	std_logic;
		daout             : out  std_logic_vector (6 downto 0));
end component msecond ;

component second is
port(
		clk, clr ,set    :  in std_logic;
			         en:    in std_logic;
		          set_clk:  in std_logic;
				set_min:    in std_logic;
		enmin              : out std_logic;
		  clkminout:  out std_logic_vector (6 downto 0);
		daout              : out std_logic_vector (6 downto 0));
end component  second ;

component  minute is
port(
		clk, clr ,set       : in  std_logic;
				 en:  in std_logic;
		set_clk:  in std_logic;
				set_hour: in std_logic;
				set_fun:  in std_logic;
                clkhourout:  out std_logic_vector (6 downto 0);
		daout             : out std_logic_vector (6 downto 0));
end component  minute;


component any_even is
generic (data_width : integer := 24 );
	port(input1 : in std_logic_vector(data_width-1 downto 0);
		 clk_in : in std_logic;
		 clk_out : out std_logic);
end component any_even;

component act is
port(
		clk, clr: in std_logic;
		second,minute,hour : in  std_logic_vector (6 downto 0);
				set_clk: in std_logic;
		dot: out std_logic;
		daout1   : out  std_logic_vector( 6 downto 0);
		sel1       : out  std_logic_vector( 5 downto 0));
end component act;


signal ensec,enmin,clkin1:std_logic;
signal sel :std_logic_vector(2 downto 0);
signal daout1,prehour,premin    :std_logic_vector(6 downto 0);
signal daout2,daout3:std_logic_vector(6 downto 0);
signal num:std_logic_vector(3 downto 0);
begin
u1: any_even port map ("100110001001011001111111",clk,clkin1);	
u2: msecond port map (clkin1,clr,set,ensec,daout1);
u3: second  port map (ensec,clr,set,en,set_clk,set_min,enmin,premin,daout2);
u4: minute  port map (enmin,clr,set,en,set_clk, set_hour,set_fun,prehour,daout3);
u5: act     port map (clk1,clr,daout1,daout2,daout3,set_clk,ss,led,selout);
process(ensec,prehour,premin,daout2,daout3)
begin
if((prehour=daout3)and(premin=daout2))then
alarm<='1';
else
alarm<='0';
end if;
end process;

end architecture behave;