_primary.vhd

来自「FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog 」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity AM is
    port(
        clk             : in     vl_logic;
        AMout           : out    vl_logic_vector(9 downto 0);
        FCW             : in     vl_logic_vector(30 downto 0);
        MCW             : in     vl_logic_vector(7 downto 0)
    );
end AM;