_primary.vhd

来自「FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog 」· VHDL 代码 · 共 8 行

library verilog;
use verilog.vl_types.all;
entity AM_tb is
    generic(
        delay           : integer := 50
    );
end AM_tb;