📄 sel_clock.rpt
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_EQ085 = !_LC1_B28 & _LC5_B26 & !_LC8_B29;
-- Node name is '|sel:11|:94'
-- Equation name is '_LC1_B29', type is buried
_LC1_B29 = LCELL( _EQ086);
_EQ086 = !_LC1_B28 & !_LC5_B26 & !_LC8_B29;
-- Node name is '|sel:11|~108~1'
-- Equation name is '_LC4_B29', type is buried
-- synthesized logic cell
!_LC4_B29 = _LC4_B29~NOT;
_LC4_B29~NOT = LCELL( _EQ087);
_EQ087 = _LC1_B28 & !_LC5_B26 & !_LC8_B29
# !_LC1_B28 & _LC5_B26 & _LC8_B29;
-- Node name is '|sel:11|:108'
-- Equation name is '_LC2_B22', type is buried
!_LC2_B22 = _LC2_B22~NOT;
_LC2_B22~NOT = LCELL( GND);
-- Node name is '|sel:11|~114~1'
-- Equation name is '_LC7_B30', type is buried
-- synthesized logic cell
_LC7_B30 = LCELL( _EQ088);
_EQ088 = _LC1_B29 & _LC3_B36
# _LC2_B29 & _LC5_B30;
-- Node name is '|sel:11|~114~2'
-- Equation name is '_LC8_B30', type is buried
-- synthesized logic cell
_LC8_B30 = LCELL( _EQ089);
_EQ089 = _LC3_B28 & _LC8_B24
# _LC7_B30;
-- Node name is '|sel:11|~114~3'
-- Equation name is '_LC2_B30', type is buried
-- synthesized logic cell
_LC2_B30 = LCELL( _EQ090);
_EQ090 = _LC1_B20 & _LC2_B28
# _LC8_B30;
-- Node name is '|sel:11|~114~4'
-- Equation name is '_LC8_B23', type is buried
-- synthesized logic cell
_LC8_B23 = LCELL( _EQ091);
_EQ091 = _LC3_B29 & _LC7_B23
# !_LC4_B29;
-- Node name is '|sel:11|:114'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ092);
_EQ092 = !_LC2_B22 & _LC2_B23
# _LC2_B30
# _LC8_B23;
-- Node name is '|sel:11|~115~1'
-- Equation name is '_LC1_B30', type is buried
-- synthesized logic cell
_LC1_B30 = LCELL( _EQ093);
_EQ093 = _LC1_B29 & _LC4_B36
# _LC2_B29 & _LC3_B25;
-- Node name is '|sel:11|~115~2'
-- Equation name is '_LC7_B28', type is buried
-- synthesized logic cell
_LC7_B28 = LCELL( _EQ094);
_EQ094 = _LC3_B28 & _LC8_B21
# _LC1_B30;
-- Node name is '|sel:11|~115~3'
-- Equation name is '_LC5_B28', type is buried
-- synthesized logic cell
_LC5_B28 = LCELL( _EQ095);
_EQ095 = _LC2_B28 & _LC3_B20
# _LC7_B28;
-- Node name is '|sel:11|~115~4'
-- Equation name is '_LC3_B22', type is buried
-- synthesized logic cell
_LC3_B22 = LCELL( _EQ096);
_EQ096 = _LC5_B28
# _LC1_B34 & _LC3_B29;
-- Node name is '|sel:11|:115'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = LCELL( _EQ097);
_EQ097 = !_LC2_B22 & _LC4_B22
# _LC3_B22;
-- Node name is '|sel:11|~116~1'
-- Equation name is '_LC6_B26', type is buried
-- synthesized logic cell
_LC6_B26 = LCELL( _EQ098);
_EQ098 = _LC2_B25 & _LC2_B29
# _LC3_B29 & _LC8_B34;
-- Node name is '|sel:11|~116~2'
-- Equation name is '_LC8_B26', type is buried
-- synthesized logic cell
_LC8_B26 = LCELL( _EQ099);
_EQ099 = _LC3_B26
# _LC1_B29 & _LC2_B26
# _LC6_B26;
-- Node name is '|sel:11|~116~3'
-- Equation name is '_LC6_B28', type is buried
-- synthesized logic cell
_LC6_B28 = LCELL( _EQ100);
_EQ100 = !_LC4_B29
# _LC2_B28 & _LC4_B20;
-- Node name is '|sel:11|~116~4'
-- Equation name is '_LC8_B28', type is buried
-- synthesized logic cell
_LC8_B28 = LCELL( _EQ101);
_EQ101 = _LC6_B28
# _LC2_B24 & _LC3_B28;
-- Node name is '|sel:11|:116'
-- Equation name is '_LC4_B26', type is buried
_LC4_B26 = LCELL( _EQ102);
_EQ102 = !_LC2_B22 & _LC4_B26
# _LC8_B26
# _LC8_B28;
-- Node name is '|sel:11|~117~1'
-- Equation name is '_LC7_B29', type is buried
-- synthesized logic cell
_LC7_B29 = LCELL( _EQ103);
_EQ103 = _LC2_B29 & _LC5_B25
# _LC1_B32 & _LC3_B29;
-- Node name is '|sel:11|~117~2'
-- Equation name is '_LC5_B29', type is buried
-- synthesized logic cell
_LC5_B29 = LCELL( _EQ104);
_EQ104 = _LC6_B29
# _LC1_B29 & _LC1_B36
# _LC7_B29;
-- Node name is '|sel:11|~117~3'
-- Equation name is '_LC4_B28', type is buried
-- synthesized logic cell
_LC4_B28 = LCELL( _EQ105);
_EQ105 = _LC2_B28 & _LC2_B32
# _LC3_B28 & _LC3_B33;
-- Node name is '|sel:11|:117'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = LCELL( _EQ106);
_EQ106 = !_LC2_B22 & _LC5_B22
# _LC5_B29
# _LC4_B28;
-- Node name is '|sel:11|~154~1'
-- Equation name is '_LC8_B22', type is buried
-- synthesized logic cell
_LC8_B22 = LCELL( _EQ107);
_EQ107 = !_LC2_B23 & _LC4_B26 & _LC5_B22;
-- Node name is '|sel:11|:268'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = LCELL( _EQ108);
_EQ108 = !_LC2_B23 & !_LC4_B22 & _LC4_B26
# _LC2_B23 & !_LC4_B22 & !_LC4_B26
# !_LC2_B23 & _LC4_B22 & !_LC4_B26
# !_LC4_B22 & _LC4_B26 & !_LC5_B22
# !_LC2_B23 & _LC4_B26 & !_LC5_B22
# _LC2_B23 & !_LC4_B22 & !_LC5_B22;
-- Node name is '|sel:11|:269'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ109);
_EQ109 = !_LC2_B23 & _LC4_B22 & !_LC4_B26
# !_LC2_B23 & _LC4_B22 & !_LC5_B22
# _LC2_B23 & !_LC4_B22 & !_LC4_B26
# !_LC2_B23 & !_LC4_B26 & !_LC5_B22;
-- Node name is '|sel:11|:270'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ110);
_EQ110 = !_LC2_B23 & _LC4_B26 & !_LC5_B22
# !_LC4_B22 & !_LC4_B26 & !_LC5_B22
# !_LC2_B23 & !_LC4_B22 & !_LC5_B22;
-- Node name is '|sel:11|:271'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ111);
_EQ111 = !_LC2_B23 & _LC4_B22 & !_LC4_B26 & _LC5_B22
# !_LC2_B23 & !_LC4_B22 & _LC4_B26
# !_LC2_B23 & _LC4_B26 & !_LC5_B22
# _LC2_B23 & !_LC4_B22 & !_LC4_B26
# !_LC2_B23 & !_LC4_B22 & !_LC5_B22;
-- Node name is '|sel:11|:272'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ112);
_EQ112 = _LC1_B19
# !_LC4_B22 & _LC8_B22
# _LC6_B22;
-- Node name is '|sel:11|~273~1'
-- Equation name is '_LC6_B22', type is buried
-- synthesized logic cell
_LC6_B22 = LCELL( _EQ113);
_EQ113 = !_LC2_B23 & !_LC4_B22 & !_LC4_B26 & _LC5_B22
# !_LC2_B23 & _LC4_B22 & _LC4_B26 & _LC5_B22;
-- Node name is '|sel:11|:273'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ114);
_EQ114 = !_LC2_B23 & _LC4_B26 & _LC5_B22
# !_LC4_B22 & !_LC4_B26
# !_LC2_B23 & !_LC4_B26 & !_LC5_B22
# !_LC2_B23 & !_LC4_B22;
-- Node name is '|sel:11|:274'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ115);
_EQ115 = _LC1_B17
# _LC4_B22 & _LC8_B22;
Project Information d:\clock\sel_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
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