📄 sel_clock.rpt
字号:
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 2 0 0 1 8 8 7 8 8 8 8 0 8 8 8 0 8 8 8 0 8 117/0
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G ^ 0 0 0 0 CLK
55 - - - -- INPUT G ^ 0 0 0 0 CLKSP
63 - - - 11 INPUT ^ 0 0 0 22 REST
62 - - - 12 INPUT ^ 0 0 0 16 S1
60 - - - 15 INPUT ^ 0 0 0 17 S2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
118 - - - 09 OUTPUT 0 1 0 0 D0
119 - - - 13 OUTPUT 0 1 0 0 D1
120 - - - 14 OUTPUT 0 1 0 0 D2
121 - - - 17 OUTPUT 0 1 0 0 D3
122 - - - 18 OUTPUT 0 1 0 0 D4
128 - - - 19 OUTPUT 0 1 0 0 D5
130 - - - 22 OUTPUT 0 1 0 0 D6
132 - - - 26 OUTPUT 0 1 0 0 SE0
133 - - - 28 OUTPUT 0 1 0 0 SE1
135 - - - 29 OUTPUT 0 1 0 0 SE2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 36 AND2 0 2 0 1 |countc:10|lpm_add_sub:571|addcore:adder|:55
- 3 - B 30 AND2 0 3 0 1 |countc:10|lpm_add_sub:572|addcore:adder|:59
- 2 - B 34 AND2 0 2 0 3 |countc:10|lpm_add_sub:573|addcore:adder|:55
- 3 - B 23 OR2 0 3 0 2 |countc:10|lpm_add_sub:573|addcore:adder|:69
- 2 - B 21 OR2 ! 0 2 0 4 |countc:10|lpm_add_sub:579|addcore:adder|:55
- 1 - B 24 OR2 0 4 0 2 |countc:10|lpm_add_sub:579|addcore:adder|:69
- 2 - B 36 OR2 ! 0 4 0 13 |countc:10|:31
- 5 - B 36 AND2 s 1 1 0 2 |countc:10|~48~1
- 8 - B 36 OR2 0 4 0 1 |countc:10|:48
- 6 - B 36 OR2 0 4 0 1 |countc:10|:49
- 1 - B 26 OR2 1 3 0 1 |countc:10|:50
- 3 - B 36 DFFE + 3 1 0 3 |countc:10|:75
- 4 - B 36 DFFE + 3 1 0 4 |countc:10|:76
- 2 - B 26 DFFE + 3 1 0 5 |countc:10|:77
- 1 - B 36 DFFE + 3 0 0 5 |countc:10|:78
- 6 - B 30 OR2 ! 0 4 0 11 |countc:10|:79
- 4 - B 30 OR2 0 4 0 1 |countc:10|:104
- 8 - B 25 OR2 s 0 4 0 1 |countc:10|~132~1
- 7 - B 25 AND2 s ! 2 1 0 3 |countc:10|~133~1
- 5 - B 30 DFFE + 3 1 0 3 |countc:10|:135
- 3 - B 25 DFFE + 1 3 0 4 |countc:10|:136
- 2 - B 25 DFFE + 1 3 0 5 |countc:10|:137
- 5 - B 25 DFFE + 1 1 0 7 |countc:10|:138
- 7 - B 34 OR2 1 3 0 1 |countc:10|:157
- 4 - B 34 OR2 1 3 0 1 |countc:10|:158
- 1 - B 23 OR2 ! 0 4 0 13 |countc:10|:160
- 4 - B 23 AND2 0 3 0 1 |countc:10|:177
- 5 - B 34 OR2 0 4 0 1 |countc:10|:187
- 7 - B 32 OR2 0 4 0 1 |countc:10|:188
- 5 - B 23 OR2 0 4 0 1 |countc:10|:199
- 6 - B 34 OR2 1 3 0 1 |countc:10|:204
- 3 - B 34 OR2 1 3 0 1 |countc:10|:205
- 6 - B 23 OR2 1 3 0 1 |countc:10|:207
- 3 - B 32 OR2 s 2 2 0 4 |countc:10|~223~1
- 7 - B 23 DFFE + 2 1 0 4 |countc:10|:225
- 1 - B 34 DFFE + 2 2 0 6 |countc:10|:226
- 8 - B 34 DFFE + 2 2 0 6 |countc:10|:227
- 1 - B 32 DFFE + 1 1 0 5 |countc:10|:228
- 2 - B 20 OR2 ! 0 4 0 9 |countc:10|:262
- 7 - B 20 OR2 s 0 3 0 1 |countc:10|~334~1
- 8 - B 20 OR2 s 0 4 0 1 |countc:10|~334~2
- 5 - B 20 AND2 s 0 3 0 2 |countc:10|~335~1
- 8 - B 32 AND2 s 0 3 0 2 |countc:10|~336~1
- 6 - B 32 OR2 s 0 4 0 1 |countc:10|~336~2
- 4 - B 32 OR2 s 0 2 0 3 |countc:10|~337~1
- 1 - B 20 DFFE + 1 3 0 2 |countc:10|:339
- 3 - B 20 DFFE + 1 3 0 4 |countc:10|:340
- 4 - B 20 DFFE + 1 3 0 5 |countc:10|:341
- 2 - B 32 DFFE + 1 1 0 7 |countc:10|:342
- 2 - B 33 OR2 ! 0 4 0 4 |countc:10|:343
- 4 - B 33 OR2 s 0 3 0 1 |countc:10|~363~1
- 6 - B 33 OR2 s 0 4 0 1 |countc:10|~444~1
- 7 - B 33 AND2 s ! 0 2 0 1 |countc:10|~445~1
- 1 - B 33 DFFE + 1 3 0 2 |countc:10|:447
- 8 - B 33 DFFE + 1 2 0 4 |countc:10|:448
- 7 - B 26 AND2 s 1 1 0 3 |countc:10|~468~1
- 4 - B 21 AND2 s 0 2 0 4 |countc:10|~493~1
- 1 - B 21 OR2 s 0 4 0 4 |countc:10|~495~1
- 3 - B 24 OR2 0 4 0 1 |countc:10|:502
- 4 - B 24 OR2 0 4 0 1 |countc:10|:528
- 5 - B 24 OR2 1 3 0 1 |countc:10|:554
- 5 - B 32 OR2 s 1 3 0 5 |countc:10|~563~1
- 5 - B 21 OR2 s 0 4 0 1 |countc:10|~563~2
- 7 - B 21 OR2 s 1 3 0 1 |countc:10|~563~3
- 3 - B 21 OR2 s 0 4 0 1 |countc:10|~564~1
- 7 - B 24 OR2 s 1 3 0 1 |countc:10|~564~2
- 5 - B 33 OR2 s ! 1 2 0 4 |countc:10|~565~1
- 8 - B 24 DFFE + 2 3 0 7 |countc:10|:567
- 8 - B 21 DFFE + 1 3 0 6 |countc:10|:568
- 2 - B 24 DFFE + 1 3 0 6 |countc:10|:569
- 3 - B 33 DFFE + 1 1 0 7 |countc:10|:570
- 8 - B 29 DFFE + 0 2 1 8 |sel:11|:37
- 1 - B 28 DFFE + 0 1 1 9 |sel:11|:38
- 5 - B 26 DFFE + 0 0 1 10 |sel:11|:39
- 3 - B 26 AND2 0 4 0 1 |sel:11|:44
- 6 - B 29 AND2 0 4 0 1 |sel:11|:45
- 3 - B 28 AND2 0 3 0 4 |sel:11|:46
- 2 - B 28 AND2 0 3 0 4 |sel:11|:62
- 3 - B 29 AND2 0 3 0 4 |sel:11|:70
- 2 - B 29 AND2 0 3 0 4 |sel:11|:86
- 1 - B 29 AND2 0 3 0 4 |sel:11|:94
- 4 - B 29 OR2 s ! 0 3 0 2 |sel:11|~108~1
- 2 - B 22 WIRE ! 0 0 0 4 |sel:11|:108
- 7 - B 30 OR2 s 0 4 0 1 |sel:11|~114~1
- 8 - B 30 OR2 s 0 3 0 1 |sel:11|~114~2
- 2 - B 30 OR2 s 0 3 0 1 |sel:11|~114~3
- 8 - B 23 OR2 s 0 3 0 1 |sel:11|~114~4
- 2 - B 23 OR2 0 3 0 7 |sel:11|:114
- 1 - B 30 OR2 s 0 4 0 1 |sel:11|~115~1
- 7 - B 28 OR2 s 0 3 0 1 |sel:11|~115~2
- 5 - B 28 OR2 s 0 3 0 1 |sel:11|~115~3
- 3 - B 22 OR2 s 0 3 0 1 |sel:11|~115~4
- 4 - B 22 OR2 0 2 0 8 |sel:11|:115
- 6 - B 26 OR2 s 0 4 0 1 |sel:11|~116~1
- 8 - B 26 OR2 s 0 4 0 1 |sel:11|~116~2
- 6 - B 28 OR2 s 0 3 0 1 |sel:11|~116~3
- 8 - B 28 OR2 s 0 3 0 1 |sel:11|~116~4
- 4 - B 26 OR2 0 3 0 7 |sel:11|:116
- 7 - B 29 OR2 s 0 4 0 1 |sel:11|~117~1
- 5 - B 29 OR2 s 0 4 0 1 |sel:11|~117~2
- 4 - B 28 OR2 s 0 4 0 1 |sel:11|~117~3
- 5 - B 22 OR2 0 3 0 7 |sel:11|:117
- 8 - B 22 AND2 s 0 3 0 2 |sel:11|~154~1
- 1 - B 22 OR2 0 4 1 0 |sel:11|:268
- 1 - B 19 OR2 0 4 1 1 |sel:11|:269
- 4 - B 17 OR2 0 4 1 0 |sel:11|:270
- 1 - B 17 OR2 0 4 1 1 |sel:11|:271
- 4 - B 13 OR2 0 4 1 0 |sel:11|:272
- 6 - B 22 OR2 s 0 4 0 1 |sel:11|~273~1
- 1 - B 13 OR2 0 4 1 0 |sel:11|:273
- 1 - B 09 OR2 0 3 1 0 |sel:11|:274
- 1 - B 25 AND2 s 2 2 0 2 S1~1
- 4 - B 25 AND2 s 0 4 0 1 S1~2
- 6 - B 25 OR2 s 0 4 0 1 S1~3
- 6 - B 21 AND2 s 0 4 0 1 S1~4
- 6 - B 20 OR2 s 0 4 0 1 S1~5
- 6 - B 24 AND2 s 0 4 0 1 S1~6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 42/144( 29%) 1/ 72( 1%) 22/ 72( 30%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 CLK
INPUT 3 CLKSP
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 22 REST
Device-Specific Information: d:\clock\sel_clock.rpt
sel_clock
** EQUATIONS **
CLK : INPUT;
CLKSP : INPUT;
REST : INPUT;
S1 : INPUT;
S2 : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC1_B9;
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