countc.rpt

EDA 数字钟实现文件 能够实现计时,闹钟,校时功能

         #  _LC3_B24;

-- Node name is '~335~1' 
-- Equation name is '~335~1', location is LC1_B24, type is buried.
-- synthesized logic cell 
_LC1_B24 = LCELL( _EQ049);
  _EQ049 =  _LC1_B22 & !_LC4_B2;

-- Node name is '~335~2' 
-- Equation name is '~335~2', location is LC4_B22, type is buried.
-- synthesized logic cell 
_LC4_B22 = LCELL( _EQ050);
  _EQ050 =  _LC1_B22 &  _LC3_B22 & !_LC4_B2;

-- Node name is '~336~1' 
-- Equation name is '~336~1', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ051);
  _EQ051 =  _LC1_B22 & !_LC5_B24
         #  _LC3_B24;

-- Node name is '~337~1' 
-- Equation name is '~337~1', location is LC3_B24, type is buried.
-- synthesized logic cell 
_LC3_B24 = LCELL( _EQ052);
  _EQ052 =  _LC4_B2
         # !_LC1_B4;

-- Node name is ':339' 
-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = DFFE( _EQ053, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ053 = !_LC2_B22 &  _LC4_B22 &  _LC6_B22
         #  _LC2_B22 &  _LC8_B22;

-- Node name is ':340' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = DFFE( _EQ054, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ054 =  _LC4_B22 & !_LC6_B22
         #  _LC6_B22 &  _LC7_B22
         #  _LC3_B24 &  _LC6_B22;

-- Node name is ':341' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = DFFE( _EQ055, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ055 =  _LC1_B24 & !_LC2_B24 &  _LC5_B24
         #  _LC2_B24 &  _LC6_B24;

-- Node name is ':342' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = DFFE( _EQ056, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ056 = !_LC3_B24 & !_LC5_B24
         #  _LC3_B24 &  _LC5_B24;

-- Node name is ':343' 
-- Equation name is '_LC8_B1', type is buried 
!_LC8_B1 = _LC8_B1~NOT;
_LC8_B1~NOT = LCELL( _EQ057);
  _EQ057 = !_LC2_B1
         #  _LC8_B12
         #  _LC1_B12
         # !_LC4_B7;

-- Node name is '~363~1' 
-- Equation name is '~363~1', location is LC1_B1, type is buried.
-- synthesized logic cell 
_LC1_B1  = LCELL( _EQ058);
  _EQ058 =  _LC2_B1
         # !_LC3_B7
         #  _LC6_B7;

-- Node name is '~444~1' 
-- Equation name is '~444~1', location is LC8_B7, type is buried.
-- synthesized logic cell 
_LC8_B7  = LCELL( _EQ059);
  _EQ059 =  _LC7_B7
         #  _LC6_B1
         # !_LC6_B7 &  _LC8_B1;

-- Node name is '~445~1' 
-- Equation name is '~445~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
_LC4_B3  = LCELL( _EQ060);
  _EQ060 = !_LC2_A10
         # !s2
         # !_LC8_B10
         # !_LC1_B4;

-- Node name is '~445~2' 
-- Equation name is '~445~2', location is LC2_B7, type is buried.
-- synthesized logic cell 
_LC2_B7  = LCELL( _EQ061);
  _EQ061 = !_LC8_B1
         # !_LC5_B22 &  s1
         #  _LC4_B3 &  s1;

-- Node name is '~445~3' 
-- Equation name is '~445~3', location is LC7_B7, type is buried.
-- synthesized logic cell 
_LC7_B7  = LCELL( _EQ062);
  _EQ062 = !_LC5_B22 &  s1
         #  _LC4_B3 &  s1;

-- Node name is ':447' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = DFFE( _EQ063, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ063 =  _LC3_B7 &  _LC8_B7
         # !_LC2_B7 & !_LC3_B7 &  _LC6_B7;

-- Node name is ':448' 
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = DFFE( _EQ064, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ064 = !_LC2_B7 & !_LC6_B7
         #  _LC2_B7 &  _LC6_B7;

-- Node name is '~468~1' 
-- Equation name is '~468~1', location is LC1_B7, type is buried.
-- synthesized logic cell 
_LC1_B7  = LCELL( _EQ065);
  _EQ065 =  _LC6_B1 & !s1;

-- Node name is '~493~1' 
-- Equation name is '~493~1', location is LC5_B7, type is buried.
-- synthesized logic cell 
_LC5_B7  = LCELL( _EQ066);
  _EQ066 =  _LC5_B22 &  _LC6_B1;

-- Node name is '~495~1' 
-- Equation name is '~495~1', location is LC6_B1, type is buried.
-- synthesized logic cell 
_LC6_B1  = LCELL( _EQ067);
  _EQ067 = !_LC8_B1 &  _LC8_B12
         # !_LC3_B5 & !_LC8_B1
         #  _LC1_B1 & !_LC8_B1;

-- Node name is ':502' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ068);
  _EQ068 =  _LC3_B1 &  _LC5_B22 &  _LC6_B1
         #  _LC2_B1 & !_LC5_B22;

-- Node name is ':528' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ069);
  _EQ069 =  _LC1_B4 &  _LC4_B1 &  _LC8_B10
         # !_LC1_B4 &  _LC2_B1
         #  _LC2_B1 & !_LC8_B10;

-- Node name is ':554' 
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ070);
  _EQ070 =  _LC2_A10 &  _LC5_B1 &  s2
         # !_LC2_A10 &  _LC2_B1
         #  _LC2_B1 & !s2;

-- Node name is '~563~1' 
-- Equation name is '~563~1', location is LC5_B12, type is buried.
-- synthesized logic cell 
_LC5_B12 = LCELL( _EQ071);
  _EQ071 = !_LC3_B5 &  _LC6_B1
         # !_LC5_B22
         #  _LC4_B3;

-- Node name is '~563~2' 
-- Equation name is '~563~2', location is LC7_B12, type is buried.
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ072);
  _EQ072 =  _LC5_B12 &  _LC8_B12 &  s1
         #  _LC6_B12 &  s1;

-- Node name is '~564~1' 
-- Equation name is '~564~1', location is LC2_B12, type is buried.
-- synthesized logic cell 
_LC2_B12 = LCELL( _EQ073);
  _EQ073 = !_LC5_B22
         #  _LC4_B3
         # !_LC4_B7 &  _LC5_B7;

-- Node name is '~564~2' 
-- Equation name is '~564~2', location is LC4_B12, type is buried.
-- synthesized logic cell 
_LC4_B12 = LCELL( _EQ074);
  _EQ074 =  _LC1_B12 &  _LC2_B12 &  s1
         #  _LC3_B12 &  s1;

-- Node name is ':567' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = DFFE( _EQ075, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ075 =  _LC7_B1 &  s1
         #  _LC3_B1 &  _LC6_B1 & !s1;

-- Node name is ':568' 
-- Equation name is '_LC8_B12', type is buried 
_LC8_B12 = DFFE( _EQ076, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ076 =  _LC7_B12
         #  _LC1_B7 &  _LC3_B5 & !_LC8_B12
         #  _LC1_B7 & !_LC3_B5 &  _LC8_B12;

-- Node name is ':569' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = DFFE( _EQ077, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ077 =  _LC4_B12
         #  _LC1_B7 &  _LC1_B12 & !_LC4_B7
         #  _LC1_B7 & !_LC1_B12 &  _LC4_B7;

-- Node name is ':570' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = DFFE( _EQ078, GLOBAL( clk), GLOBAL( rest),  VCC,  VCC);
  _EQ078 = !_LC4_B3 & !_LC4_B7 &  _LC5_B22
         # !_LC4_B7 & !s1
         #  _LC4_B7 & !_LC5_B22 &  s1
         #  _LC4_B3 &  _LC4_B7 &  s1;



Project Information                                        d:\clock\countc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 26,659K