📄 countc.rpt
字号:
96 - - - 22 OUTPUT 0 1 0 0 minh3
13 - - B -- OUTPUT 0 1 0 0 minl0
65 - - B -- OUTPUT 0 1 0 0 minl1
64 - - B -- OUTPUT 0 1 0 0 minl2
80 - - - 03 OUTPUT 0 1 0 0 minl3
46 - - - 10 OUTPUT 0 1 0 0 sech0
86 - - - 09 OUTPUT 0 1 0 0 sech1
47 - - - 09 OUTPUT 0 1 0 0 sech2
15 - - B -- OUTPUT 0 1 0 0 sech3
70 - - A -- OUTPUT 0 1 0 0 secl0
71 - - A -- OUTPUT 0 1 0 0 secl1
69 - - A -- OUTPUT 0 1 0 0 secl2
68 - - A -- OUTPUT 0 1 0 0 secl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\clock\countc.rpt
countc
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 10 AND2 0 2 0 1 |lpm_add_sub:571|addcore:adder|:55
- 5 - B 10 AND2 0 2 0 2 |lpm_add_sub:572|addcore:adder|:55
- 1 - B 10 OR2 0 4 0 1 |lpm_add_sub:572|addcore:adder|:69
- 5 - B 03 AND2 0 2 0 2 |lpm_add_sub:573|addcore:adder|:55
- 3 - B 04 OR2 0 4 0 2 |lpm_add_sub:573|addcore:adder|:69
- 3 - B 22 OR2 ! 0 2 0 3 |lpm_add_sub:575|addcore:adder|:55
- 3 - B 05 OR2 ! 0 2 0 4 |lpm_add_sub:579|addcore:adder|:55
- 3 - B 01 OR2 0 4 0 2 |lpm_add_sub:579|addcore:adder|:69
- 3 - B 12 AND2 s 0 4 0 1 s1~1
- 6 - B 12 AND2 s 0 4 0 1 s1~2
- 7 - B 22 AND2 s 0 2 0 1 s1~3
- 8 - B 02 AND2 s 2 2 0 2 s1~4
- 2 - A 10 OR2 ! 0 4 0 12 :31
- 3 - B 02 AND2 s 1 1 0 3 ~48~1
- 8 - A 10 OR2 0 4 0 1 :48
- 4 - A 10 OR2 0 4 0 1 :49
- 3 - A 10 OR2 0 3 0 1 :50
- 6 - A 10 DFFE + 2 1 1 2 :75
- 5 - A 10 DFFE + 2 1 1 3 :76
- 1 - A 10 DFFE + 2 1 1 4 :77
- 2 - B 02 DFFE + 2 0 1 4 :78
- 8 - B 10 OR2 ! 0 4 0 11 :79
- 6 - B 02 OR2 0 4 0 1 :104
- 7 - B 10 OR2 s 0 4 0 1 ~131~1
- 4 - B 10 OR2 s 0 4 0 1 ~132~1
- 1 - B 02 AND2 s ! 2 1 0 3 ~133~1
- 5 - B 02 DFFE + 2 1 1 3 :135
- 6 - B 10 DFFE + 0 3 1 2 :136
- 3 - B 10 DFFE + 0 3 1 3 :137
- 2 - B 10 DFFE + 0 1 1 5 :138
- 1 - B 04 OR2 ! 0 4 0 10 :139
- 8 - B 03 OR2 1 3 0 1 :157
- 3 - B 03 OR2 1 3 0 1 :158
- 6 - B 04 AND2 0 3 0 1 :177
- 6 - B 03 OR2 0 4 0 1 :187
- 2 - B 04 OR2 0 4 0 1 :188
- 7 - B 04 OR2 0 4 0 1 :199
- 7 - B 03 OR2 1 3 0 1 :204
- 5 - B 04 OR2 1 3 0 1 :205
- 8 - B 04 OR2 1 3 0 1 :207
- 4 - B 02 OR2 s 2 2 0 4 ~223~1
- 4 - B 04 DFFE + 1 1 1 3 :225
- 2 - B 03 DFFE + 1 2 1 5 :226
- 1 - B 03 DFFE + 1 2 1 6 :227
- 4 - B 24 DFFE + 0 1 1 5 :228
- 5 - B 22 OR2 ! 0 4 0 8 :229
- 1 - B 22 AND2 s 0 2 0 5 ~245~1
- 8 - B 22 OR2 s 0 4 0 1 ~334~1
- 1 - B 24 AND2 s 0 2 0 1 ~335~1
- 4 - B 22 AND2 s 0 3 0 2 ~335~2
- 6 - B 24 OR2 s 0 3 0 1 ~336~1
- 3 - B 24 OR2 s 0 2 0 4 ~337~1
- 2 - B 22 DFFE + 0 3 1 1 :339
- 6 - B 22 DFFE + 0 3 1 3 :340
- 2 - B 24 DFFE + 0 3 1 2 :341
- 5 - B 24 DFFE + 0 1 1 4 :342
- 8 - B 01 OR2 ! 0 4 0 3 :343
- 1 - B 01 OR2 s 0 3 0 1 ~363~1
- 8 - B 07 OR2 s 0 4 0 1 ~444~1
- 4 - B 03 OR2 s 1 3 0 7 ~445~1
- 2 - B 07 OR2 s 1 3 0 2 ~445~2
- 7 - B 07 OR2 s 1 2 0 1 ~445~3
- 3 - B 07 DFFE + 0 3 1 1 :447
- 6 - B 07 DFFE + 0 1 1 3 :448
- 1 - B 07 AND2 s 1 1 0 2 ~468~1
- 5 - B 07 AND2 s 0 2 0 3 ~493~1
- 6 - B 01 OR2 s 0 4 0 6 ~495~1
- 4 - B 01 OR2 0 4 0 1 :502
- 5 - B 01 OR2 0 4 0 1 :528
- 7 - B 01 OR2 1 3 0 1 :554
- 5 - B 12 OR2 s 0 4 0 1 ~563~1
- 7 - B 12 OR2 s 1 3 0 1 ~563~2
- 2 - B 12 OR2 s 0 4 0 1 ~564~1
- 4 - B 12 OR2 s 1 3 0 1 ~564~2
- 2 - B 01 DFFE + 1 3 1 6 :567
- 8 - B 12 DFFE + 0 3 1 5 :568
- 1 - B 12 DFFE + 0 3 1 5 :569
- 4 - B 07 DFFE + 1 2 1 6 :570
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\clock\countc.rpt
countc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 31/ 96( 32%) 6/ 48( 12%) 3/ 48( 6%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\clock\countc.rpt
countc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 clk
Device-Specific Information: d:\clock\countc.rpt
countc
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 22 rest
Device-Specific Information: d:\clock\countc.rpt
countc
** EQUATIONS **
clk : INPUT;
rest : INPUT;
s1 : INPUT;
s2 : INPUT;
-- Node name is 'hourh0'
-- Equation name is 'hourh0', type is output
hourh0 = _LC6_B7;
-- Node name is 'hourh1'
-- Equation name is 'hourh1', type is output
hourh1 = _LC3_B7;
-- Node name is 'hourl0'
-- Equation name is 'hourl0', type is output
hourl0 = _LC4_B7;
-- Node name is 'hourl1'
-- Equation name is 'hourl1', type is output
hourl1 = _LC1_B12;
-- Node name is 'hourl2'
-- Equation name is 'hourl2', type is output
hourl2 = _LC8_B12;
-- Node name is 'hourl3'
-- Equation name is 'hourl3', type is output
hourl3 = _LC2_B1;
-- Node name is 'minh0'
-- Equation name is 'minh0', type is output
minh0 = _LC5_B24;
-- Node name is 'minh1'
-- Equation name is 'minh1', type is output
minh1 = _LC2_B24;
-- Node name is 'minh2'
-- Equation name is 'minh2', type is output
minh2 = _LC6_B22;
-- Node name is 'minh3'
-- Equation name is 'minh3', type is output
minh3 = _LC2_B22;
-- Node name is 'minl0'
-- Equation name is 'minl0', type is output
minl0 = _LC4_B24;
-- Node name is 'minl1'
-- Equation name is 'minl1', type is output
minl1 = _LC1_B3;
-- Node name is 'minl2'
-- Equation name is 'minl2', type is output
minl2 = _LC2_B3;
-- Node name is 'minl3'
-- Equation name is 'minl3', type is output
minl3 = _LC4_B4;
-- Node name is 'sech0'
-- Equation name is 'sech0', type is output
sech0 = _LC2_B10;
-- Node name is 'sech1'
-- Equation name is 'sech1', type is output
sech1 = _LC3_B10;
-- Node name is 'sech2'
-- Equation name is 'sech2', type is output
sech2 = _LC6_B10;
-- Node name is 'sech3'
-- Equation name is 'sech3', type is output
sech3 = _LC5_B2;
-- Node name is 'secl0'
-- Equation name is 'secl0', type is output
secl0 = _LC2_B2;
-- Node name is 'secl1'
-- Equation name is 'secl1', type is output
secl1 = _LC1_A10;
-- Node name is 'secl2'
-- Equation name is 'secl2', type is output
secl2 = _LC5_A10;
-- Node name is 'secl3'
-- Equation name is 'secl3', type is output
secl3 = _LC6_A10;
-- Node name is 's1~1'
-- Equation name is 's1~1', location is LC3_B12, type is buried.
-- synthesized logic cell
_LC3_B12 = LCELL( _EQ001);
_EQ001 = !_LC1_B12 & !_LC4_B3 & _LC4_B7 & _LC5_B7;
-- Node name is 's1~2'
-- Equation name is 's1~2', location is LC6_B12, type is buried.
-- synthesized logic cell
_LC6_B12 = LCELL( _EQ002);
_EQ002 = _LC3_B5 & !_LC4_B3 & _LC5_B7 & !_LC8_B12;
-- Node name is 's1~3'
-- Equation name is 's1~3', location is LC7_B22, type is buried.
-- synthesized logic cell
_LC7_B22 = LCELL( _EQ003);
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