sel.rpt

EDA 数字钟实现文件 能够实现计时,闹钟,校时功能

_LC7_B14 = LCELL( _EQ013);
  _EQ013 =  _LC4_B24 &  minh3
         #  _LC5_B14;

-- Node name is '~114~4' 
-- Equation name is '~114~4', location is LC8_B14, type is buried.
-- synthesized logic cell 
_LC8_B14 = LCELL( _EQ014);
  _EQ014 =  _LC1_B16 &  minl3
         # !_LC8_B22;

-- Node name is ':114' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = LCELL( _EQ015);
  _EQ015 =  _LC1_B14 & !_LC3_B22
         #  _LC7_B14
         #  _LC8_B14;

-- Node name is '~115~1' 
-- Equation name is '~115~1', location is LC4_B16, type is buried.
-- synthesized logic cell 
_LC4_B16 = LCELL( _EQ016);
  _EQ016 =  _LC5_B22 &  secl2
         #  _LC2_B16 &  sech2;

-- Node name is '~115~2' 
-- Equation name is '~115~2', location is LC5_B16, type is buried.
-- synthesized logic cell 
_LC5_B16 = LCELL( _EQ017);
  _EQ017 =  hourl2 &  _LC3_B24
         #  _LC4_B16;

-- Node name is '~115~3' 
-- Equation name is '~115~3', location is LC7_B16, type is buried.
-- synthesized logic cell 
_LC7_B16 = LCELL( _EQ018);
  _EQ018 =  _LC4_B24 &  minh2
         #  _LC5_B16;

-- Node name is '~115~4' 
-- Equation name is '~115~4', location is LC8_B16, type is buried.
-- synthesized logic cell 
_LC8_B16 = LCELL( _EQ019);
  _EQ019 =  _LC7_B16
         #  _LC1_B16 &  minl2;

-- Node name is ':115' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ020);
  _EQ020 =  _LC3_B16 & !_LC3_B22
         #  _LC8_B16;

-- Node name is '~116~1' 
-- Equation name is '~116~1', location is LC3_B14, type is buried.
-- synthesized logic cell 
_LC3_B14 = LCELL( _EQ021);
  _EQ021 =  _LC2_B16 &  sech1
         #  _LC1_B16 &  minl1;

-- Node name is '~116~2' 
-- Equation name is '~116~2', location is LC2_B22, type is buried.
-- synthesized logic cell 
_LC2_B22 = LCELL( _EQ022);
  _EQ022 =  _LC1_B22
         #  _LC5_B22 &  secl1
         #  _LC3_B14;

-- Node name is '~116~3' 
-- Equation name is '~116~3', location is LC6_B22, type is buried.
-- synthesized logic cell 
_LC6_B22 = LCELL( _EQ023);
  _EQ023 = !_LC8_B22
         #  _LC4_B24 &  minh1;

-- Node name is '~116~4' 
-- Equation name is '~116~4', location is LC7_B22, type is buried.
-- synthesized logic cell 
_LC7_B22 = LCELL( _EQ024);
  _EQ024 =  _LC6_B22
         #  hourl1 &  _LC3_B24;

-- Node name is ':116' 
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = LCELL( _EQ025);
  _EQ025 = !_LC3_B22 &  _LC4_B22
         #  _LC2_B22
         #  _LC7_B22;

-- Node name is '~117~1' 
-- Equation name is '~117~1', location is LC2_B14, type is buried.
-- synthesized logic cell 
_LC2_B14 = LCELL( _EQ026);
  _EQ026 =  _LC2_B16 &  sech0
         #  _LC1_B16 &  minl0;

-- Node name is '~117~2' 
-- Equation name is '~117~2', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ027);
  _EQ027 =  _LC5_B24
         #  _LC5_B22 &  secl0
         #  _LC2_B14;

-- Node name is '~117~3' 
-- Equation name is '~117~3', location is LC7_B24, type is buried.
-- synthesized logic cell 
_LC7_B24 = LCELL( _EQ028);
  _EQ028 =  _LC4_B24 &  minh0
         #  hourl0 &  _LC3_B24;

-- Node name is ':117' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = LCELL( _EQ029);
  _EQ029 =  _LC1_B24 & !_LC3_B22
         #  _LC6_B24
         #  _LC7_B24;

-- Node name is '~154~1' 
-- Equation name is '~154~1', location is LC3_B21, type is buried.
-- synthesized logic cell 
_LC3_B21 = LCELL( _EQ030);
  _EQ030 = !_LC1_B14 &  _LC1_B24 &  _LC4_B22;

-- Node name is ':268' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = LCELL( _EQ031);
  _EQ031 = !_LC1_B14 & !_LC3_B16 &  _LC4_B22
         #  _LC1_B14 & !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 &  _LC3_B16 & !_LC4_B22
         # !_LC1_B24 & !_LC3_B16 &  _LC4_B22
         # !_LC1_B14 & !_LC1_B24 &  _LC4_B22
         #  _LC1_B14 & !_LC1_B24 & !_LC3_B16;

-- Node name is ':269' 
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = LCELL( _EQ032);
  _EQ032 = !_LC1_B14 &  _LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC1_B24 &  _LC3_B16
         #  _LC1_B14 & !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC1_B24 & !_LC4_B22;

-- Node name is ':270' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ033);
  _EQ033 = !_LC1_B14 & !_LC1_B24 &  _LC4_B22
         # !_LC1_B24 & !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC1_B24 & !_LC3_B16;

-- Node name is ':271' 
-- Equation name is '_LC7_B21', type is buried 
_LC7_B21 = LCELL( _EQ034);
  _EQ034 = !_LC1_B14 &  _LC1_B24 &  _LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC3_B16 &  _LC4_B22
         # !_LC1_B14 & !_LC1_B24 &  _LC4_B22
         #  _LC1_B14 & !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC1_B24 & !_LC3_B16;

-- Node name is ':272' 
-- Equation name is '_LC1_B21', type is buried 
_LC1_B21 = LCELL( _EQ035);
  _EQ035 =  _LC4_B21
         # !_LC3_B16 &  _LC3_B21
         #  _LC6_B21;

-- Node name is '~273~1' 
-- Equation name is '~273~1', location is LC6_B21, type is buried.
-- synthesized logic cell 
_LC6_B21 = LCELL( _EQ036);
  _EQ036 = !_LC1_B14 &  _LC1_B24 & !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 &  _LC1_B24 &  _LC3_B16 &  _LC4_B22;

-- Node name is ':273' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ037);
  _EQ037 = !_LC1_B14 &  _LC1_B24 &  _LC4_B22
         # !_LC3_B16 & !_LC4_B22
         # !_LC1_B14 & !_LC1_B24 & !_LC4_B22
         # !_LC1_B14 & !_LC3_B16;

-- Node name is ':274' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ038);
  _EQ038 =  _LC7_B21
         #  _LC3_B16 &  _LC3_B21;



Project Information                                           d:\clock\sel.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 28,874K