📄 sel.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\clock\sel.rpt
sel
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 24 DFFE + 0 2 1 8 :37
- 6 - B 16 DFFE + 0 1 1 9 :38
- 8 - B 24 DFFE + 0 0 1 10 :39
- 1 - B 22 AND2 1 3 0 1 :44
- 5 - B 24 AND2 1 3 0 1 :45
- 3 - B 24 AND2 0 3 0 4 :46
- 4 - B 24 AND2 0 3 0 4 :62
- 1 - B 16 AND2 0 3 0 4 :70
- 2 - B 16 AND2 0 3 0 4 :86
- 5 - B 22 AND2 0 3 0 4 :94
- 8 - B 22 OR2 s ! 0 3 0 2 ~108~1
- 3 - B 22 WIRE ! 0 0 0 4 :108
- 4 - B 14 OR2 s 2 2 0 1 ~114~1
- 5 - B 14 OR2 s 1 2 0 1 ~114~2
- 7 - B 14 OR2 s 1 2 0 1 ~114~3
- 8 - B 14 OR2 s 1 2 0 1 ~114~4
- 1 - B 14 OR2 0 3 0 7 :114
- 4 - B 16 OR2 s 2 2 0 1 ~115~1
- 5 - B 16 OR2 s 1 2 0 1 ~115~2
- 7 - B 16 OR2 s 1 2 0 1 ~115~3
- 8 - B 16 OR2 s 1 2 0 1 ~115~4
- 3 - B 16 OR2 0 2 0 8 :115
- 3 - B 14 OR2 s 2 2 0 1 ~116~1
- 2 - B 22 OR2 s 1 3 0 1 ~116~2
- 6 - B 22 OR2 s 1 2 0 1 ~116~3
- 7 - B 22 OR2 s 1 2 0 1 ~116~4
- 4 - B 22 OR2 0 3 0 7 :116
- 2 - B 14 OR2 s 2 2 0 1 ~117~1
- 6 - B 24 OR2 s 1 3 0 1 ~117~2
- 7 - B 24 OR2 s 2 2 0 1 ~117~3
- 1 - B 24 OR2 0 3 0 7 :117
- 3 - B 21 AND2 s 0 3 0 2 ~154~1
- 8 - B 21 OR2 0 4 1 0 :268
- 4 - B 21 OR2 0 4 1 1 :269
- 2 - B 21 OR2 0 4 1 0 :270
- 7 - B 21 OR2 0 4 1 1 :271
- 1 - B 21 OR2 0 4 1 0 :272
- 6 - B 21 OR2 s 0 4 0 1 ~273~1
- 6 - B 14 OR2 0 4 1 0 :273
- 5 - B 21 OR2 0 3 1 0 :274
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\clock\sel.rpt
sel
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 16/ 96( 16%) 0/ 48( 0%) 20/ 48( 41%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\clock\sel.rpt
sel
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clksp
Device-Specific Information: d:\clock\sel.rpt
sel
** EQUATIONS **
clksp : INPUT;
hourh0 : INPUT;
hourh1 : INPUT;
hourl0 : INPUT;
hourl1 : INPUT;
hourl2 : INPUT;
hourl3 : INPUT;
minh0 : INPUT;
minh1 : INPUT;
minh2 : INPUT;
minh3 : INPUT;
minl0 : INPUT;
minl1 : INPUT;
minl2 : INPUT;
minl3 : INPUT;
sech0 : INPUT;
sech1 : INPUT;
sech2 : INPUT;
sech3 : INPUT;
secl0 : INPUT;
secl1 : INPUT;
secl2 : INPUT;
secl3 : INPUT;
-- Node name is 'Display0'
-- Equation name is 'Display0', type is output
Display0 = _LC5_B21;
-- Node name is 'Display1'
-- Equation name is 'Display1', type is output
Display1 = _LC6_B14;
-- Node name is 'Display2'
-- Equation name is 'Display2', type is output
Display2 = _LC1_B21;
-- Node name is 'Display3'
-- Equation name is 'Display3', type is output
Display3 = _LC7_B21;
-- Node name is 'Display4'
-- Equation name is 'Display4', type is output
Display4 = _LC2_B21;
-- Node name is 'Display5'
-- Equation name is 'Display5', type is output
Display5 = _LC4_B21;
-- Node name is 'Display6'
-- Equation name is 'Display6', type is output
Display6 = _LC8_B21;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC8_B24;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC6_B16;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC2_B24;
-- Node name is ':37'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE( _EQ001, GLOBAL( clksp), VCC, VCC, VCC);
_EQ001 = _LC2_B24 & !_LC6_B16
# _LC2_B24 & !_LC8_B24
# !_LC2_B24 & _LC6_B16 & _LC8_B24;
-- Node name is ':38'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE( _EQ002, GLOBAL( clksp), VCC, VCC, VCC);
_EQ002 = _LC6_B16 & !_LC8_B24
# !_LC6_B16 & _LC8_B24;
-- Node name is ':39'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = DFFE(!_LC8_B24, GLOBAL( clksp), VCC, VCC, VCC);
-- Node name is ':44'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = LCELL( _EQ003);
_EQ003 = hourh1 & _LC2_B24 & _LC6_B16 & _LC8_B24;
-- Node name is ':45'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ004);
_EQ004 = hourh0 & _LC2_B24 & _LC6_B16 & _LC8_B24;
-- Node name is ':46'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ005);
_EQ005 = _LC2_B24 & _LC6_B16 & !_LC8_B24;
-- Node name is ':62'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ006);
_EQ006 = _LC2_B24 & !_LC6_B16 & !_LC8_B24;
-- Node name is ':70'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ007);
_EQ007 = !_LC2_B24 & _LC6_B16 & _LC8_B24;
-- Node name is ':86'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ008);
_EQ008 = !_LC2_B24 & !_LC6_B16 & _LC8_B24;
-- Node name is ':94'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = LCELL( _EQ009);
_EQ009 = !_LC2_B24 & !_LC6_B16 & !_LC8_B24;
-- Node name is '~108~1'
-- Equation name is '~108~1', location is LC8_B22, type is buried.
-- synthesized logic cell
!_LC8_B22 = _LC8_B22~NOT;
_LC8_B22~NOT = LCELL( _EQ010);
_EQ010 = !_LC2_B24 & _LC6_B16 & !_LC8_B24
# _LC2_B24 & !_LC6_B16 & _LC8_B24;
-- Node name is ':108'
-- Equation name is '_LC3_B22', type is buried
!_LC3_B22 = _LC3_B22~NOT;
_LC3_B22~NOT = LCELL( GND);
-- Node name is '~114~1'
-- Equation name is '~114~1', location is LC4_B14, type is buried.
-- synthesized logic cell
_LC4_B14 = LCELL( _EQ011);
_EQ011 = _LC5_B22 & secl3
# _LC2_B16 & sech3;
-- Node name is '~114~2'
-- Equation name is '~114~2', location is LC5_B14, type is buried.
-- synthesized logic cell
_LC5_B14 = LCELL( _EQ012);
_EQ012 = hourl3 & _LC3_B24
# _LC4_B14;
-- Node name is '~114~3'
-- Equation name is '~114~3', location is LC7_B14, type is buried.
-- synthesized logic cell
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