countc.v

EDA 数字钟实现文件 能够实现计时,闹钟,校时功能

module countc (clk,rest,secl,sech,minl,minh,hourl,hourh,s1,s2);
 input clk;
 input rest;
 input s1;
 input s2;
 output [3:0] secl;
 output [3:0] sech;
 output [3:0] minl;
 output [3:0] minh;
 output [3:0] hourl;
 output [1:0] hourh;
 reg [3:0] secl;
 reg [3:0] sech;
 reg [3:0] minl;
 reg [3:0] minh;
 reg [3:0] hourl;
 reg [1:0] hourh;
 reg [13:0] clk_count1;
 reg clk_1hz;


//always @ (posedge clk)
//begin
 //if(clk_count1==9999) //对计数器进行判断, 以确定Clk_1HZ 信号是否反转
  //begin
   //clk_count1<=0;
   //clk_1hz<=~clk_1hz;
  //end
 //else clk_count1<=clk_count1+1;
//end


always @ (posedge clk or negedge rest) 
if(! rest)//系统复位
 begin
  secl<=0;
  sech<=0;
  minl<=0;
  minh<=0;
  hourl<=0;
  hourh<=0;
 end
else
 begin
 if(! s1) //调节小时
  begin
   if(hourl==9)
     begin
       hourl<=0;
       hourh<=hourh+1;
     end
  else
    begin
      if(hourh==2 && hourl==3)
        begin
         hourl<=0;
         hourh<=0;
        end
      else
       hourl<=hourl+1;
    end
  end
else if(! s2)
      begin
      if(minl==9)
        begin
         minl<=0;
         if(minh==5) minh<=0;
         else minh<=minh+1;
        end
         else minl<=minl+1;
      end
 else if(secl==9) //一般运行状态
      begin
         secl<=0;
           if(sech==5)
             begin
              sech<=0;
              if(minl==9)
                begin
                 minl <= 0;
                  if(minh==5)
                       begin
                          minh<=0;
                          if(hourl==9)
                          begin
                             hourl<=0;
                             hourh<=hourh+1;
                          end
                          else if(hourh==2 && hourl==3)
                             begin
                             hourl<=0;
                             hourh<=0;
                            end 
                            else hourl<=hourl+1;
                       end
                    else minh<=minh+1;
                  end
                 else minl<=minl+1;
               end
             else sech<=sech+1;
           end
         else secl<=secl+1;
        end
endmodule