dds_new.hif

驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级

PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
areset
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
d:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
d:|altera|72|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
d:|altera|72|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
d:|altera|72|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
pll4:inst4|altpll:altpll_component
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sinrom
# storage
db|dds_new.(9).cnf
db|dds_new.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sinrom.v
5aa4d09bf313bdf396d9e5b16d82293
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
sinrom:inst3
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram
# storage
db|dds_new.(10).cnf
db|dds_new.(10).cnf
# case_insensitive
# source_file
d:|altera|72|quartus|libraries|megafunctions|altsyncram.tdf
56e814d9f431d4c82859865aa9372
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
14
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
16384
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5071
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
rden_a
-1
2
data_b
-1
2
data_a
-1
2
clocken3
-1
2
clocken2
-1
2
clocken1
-1
2
clocken0
-1
2
clock1
-1
2
byteena_b
-1
2
byteena_a
-1
2
address_b
-1
2
}
# include_file {
d:|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
d:|altera|72|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|altera|72|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|72|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|altera|72|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|altera|72|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|altera|72|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|altera|72|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
d:|altera|72|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram_5071
# storage
db|dds_new.(11).cnf
db|dds_new.(11).cnf
# case_insensitive
# source_file
db|altsyncram_5071.tdf
872574297f27c65f3aea95d58dc6d9a1
6
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
rom.mif
c838f13b6b83ce780eb9e4fc6d1e2fd
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
decode_4oa
# storage
db|dds_new.(12).cnf
db|dds_new.(12).cnf
# case_insensitive
# source_file
db|decode_4oa.tdf
8c10f06e41af94ed9cd23e2af1e6c141
6
# used_port {
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
data1
-1
3
data0
-1
3
enable
-1
2
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|decode_4oa:deep_decode
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
mux_vjb
# storage
db|dds_new.(13).cnf
db|dds_new.(13).cnf
# case_insensitive
# source_file
db|mux_vjb.tdf
953fdb5abb5803dc56460f09eaafb80
6
# used_port {
sel1
-1
3
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data47
-1
3
data46
-1
3
data45
-1
3
data44
-1
3
data43
-1
3
data42
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
sinrom:inst3|altsyncram:altsyncram_component|altsyncram_5071:auto_generated|mux_vjb:mux2
}
# lmf
d:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete