prev_cmp_dds_new.tan.qmsg

来自「驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率」· QMSG 代码 · 共 8 行 · 第 1/5 页

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll4:inst4\|altpll:altpll_component\|_clk0 register acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\] register acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\] 795 ps " "Info: Minimum slack time is 795 ps for clock \"pll4:inst4\|altpll:altpll_component\|_clk0\" between source register \"acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\]\" and destination register \"acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.811 ns + Shortest register register " "Info: + Shortest register to register delay is 0.811 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\] 1 REG LCFF_X23_Y8_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y8_N1; Fanout = 4; REG Node = 'acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto_generated|pipeline_dffe[16] } "NODE_NAME" } } { "db/add_sub_q4h.tdf" "" { Text "D:/Project/dds_new/db/add_sub_q4h.tdf" 31 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.420 ns) 0.727 ns acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\]~225 2 COMB LCCOMB_X23_Y8_N0 1 " "Info: 2: + IC(0.307 ns) + CELL(0.420 ns) = 0.727 ns; Loc. = LCCOMB_X23_Y8_N0; Fanout = 1; COMB Node = 'acc:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_q4h:auto_generated\|pipeline_dffe\[16\]~225'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.727 ns" { acc:inst|lpm_add_sub:lpm_add_sub_component|add_sub_q4h:auto