dds_new.fit.rpt

驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级

+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Project/dds_new/dds_new.pin.


+-------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                       ;
+---------------------------------------------+---------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                 ;
+---------------------------------------------+---------------------------------------------------------------------------------------+
; Total logic elements                        ; 92 / 33,216 ( < 1 % )                                                                 ;
;     -- Combinational with no register       ; 56                                                                                    ;
;     -- Register only                        ; 0                                                                                     ;
;     -- Combinational with a register        ; 36                                                                                    ;
;                                             ;                                                                                       ;
; Logic element usage by number of LUT inputs ;                                                                                       ;
;     -- 4 input functions                    ; 24                                                                                    ;
;     -- 3 input functions                    ; 62                                                                                    ;
;     -- <=2 input functions                  ; 6                                                                                     ;
;     -- Register only                        ; 0                                                                                     ;
;                                             ;                                                                                       ;
; Logic elements by mode                      ;                                                                                       ;
;     -- normal mode                          ; 30                                                                                    ;
;     -- arithmetic mode                      ; 62                                                                                    ;
;                                             ;                                                                                       ;
; Total registers*                            ; 36 / 34,593 ( < 1 % )                                                                 ;
;     -- Dedicated logic registers            ; 36 / 33,216 ( < 1 % )                                                                 ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )                                                                     ;
;                                             ;                                                                                       ;
; Total LABs:  partially or completely used   ; 10 / 2,076 ( < 1 % )                                                                  ;
; User inserted logic elements                ; 0                                                                                     ;
; Virtual pins                                ; 0                                                                                     ;
; I/O pins                                    ; 110 / 475 ( 23 % )                                                                    ;
;     -- Clock pins                           ; 2 / 8 ( 25 % )                                                                        ;
; Global signals                              ; 2                                                                                     ;
; M4Ks                                        ; 48 / 105 ( 46 % )                                                                     ;
; Total memory bits                           ; 196,608 / 483,840 ( 41 % )                                                            ;